Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2002-01-09
2004-09-07
Vinh, Lan (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S710000, C438S712000, C438S720000, C216S058000, C216S067000
Reexamination Certificate
active
06787474
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATION
This application is based on Japanese patent application 2001-300562, filed on Sep. 28, 2001, the whole contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
A) Field of the Invention
The present invention relates to a manufacture method for semiconductor devices, and more particularly to a semiconductor device manufacture method having a process of dry-etching a silicon-containing insulating film by using the underlying film as an etching stopper film.
B) Description of the Related Art
In order to connect wiring patterns formed on an interlayer insulating film to the source/drain regions of MOSFET covered with the interlayer insulating film, contact holes are formed through the interlayer insulating film. Generally, there is dispersion of thicknesses of interlayer insulating films. Contact holes for the source/drain regions and a contact hole for the gate electrode are formed at the same time in some cases. An interlayer insulating film formed on the source/drain regions is usually thicker than an interlayer insulating film on the gate electrode.
An over-etch is usually performed in order to form a contact even through a thick region of an interlayer insulating film with good reproductivity. In order to prevent damages of the source/drain regions to be caused by over-etch, an etching stopper made of material having an etching rate slower than an interlayer insulating film is disposed on the surface of an underlying film of the interlayer insulating film. If the interlayer insulating film is made of silicon oxide (SiO
2
), the etching stopper film is made of, for example, silicon nitride (SiN).
Since the patterns of semiconductor integrated circuit devices are becoming finer, contact holes are formed in a self alignment manner (Self-Aligned contact: SAC). With this SAC method, the side walls and upper surface of a gate electrode are covered with an etching stopper film, and an interlayer insulating film is formed on the etching stopper film. The etching stopper film protects the gate electrode while contact holes are formed through the interlayer insulating film to expose the surfaces of the source/drain regions, so that the gate electrode is prevented from being exposed.
When a multi-layer wiring structure of Al wiring patterns is formed, an antioxidation TiN film or antireflection SiON film is formed on an Al wiring layer. While via holes are formed through an interlayer insulating film, this TiN film or SiON film functions as an etching stopper film.
In order to stop etching at such an etching stopper film with good reproductivity, it is necessary to obtain a high etching rate ratio (selection ratio) between the interlayer insulating film and etching stopper film. Conventionally, carbon monoxide (CO) is added to C
4
F
8
to realize a high selection ratio.
Techniques of forming a Cu wiring by a damascene method has recently been used in order to lower a wiring resistance and improve the performance of the semiconductor device. With a single damascene method, a via layer insulating film is formed on an underlying Cu wring, and a via hole is formed through this via layer insulating film. After the via hole is formed, the resist pattern used as an etching mask is ashed and removed by using oxygen plasma.
If the underlying Cu wiring is exposed while the resist pattern is ashed, the Cu wiring is oxidized. In order to avoid this, the upper surface of the Cu wiring is usually protected by an antioxidation film made of silicon nitride or the like. While the antioxidation film is left on the bottom of the via hole, the resist pattern is ashed. This antioxidation film also functions as an etching stopper film while the via hole is formed. After the resist pattern is removed, the antioxidation film left on the bottom of the via hole is etched to expose the Cu wiring.
Instability of an etching system, dispersion of thicknesses of interlayer insulating films, variation in etching rates in the whole area of a substrate, and the like may result in over-etch while via holes are formed. An etching rate of a via hole having a high aspect ratio becomes slow because of the micro loading effect.
An antimoisture ring made of metal is usually disposed around the outer peripheral area of a chip. At the same time when a via hole is formed, a groove pattern for disposing an antimoisture ring is formed in the outer peripheral area of the chip. This groove pattern has an aspect ratio lower than that of the via hole so that the etching rate of the groove pattern becomes faster than that of the via hole. An over-etch amount of the groove pattern becomes therefore large.
Wiring groove patterns to be formed by the damascene method have various sizes and aspect ratios. A large over-etch occurs in a groove pattern having a relatively large aspect ratio.
In order to leave an antioxidation film with good reproductivity on the bottom of a via hole or groove pattern which may be subjected to large over-etch, the via hole or groove pattern is required to be formed under the etching conditions of a large selection ratio between a via layer insulating film or wiring layer insulating film and the etching stopper film.
Conventional etching techniques cannot obtain a sufficiently high selection ratio so that an etching stopper film on the bottom of a via hole or groove pattern is likely to be etched and removed by over-etch and the Cu wiring is oxidized.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method of manufacturing a semiconductor device by utilizing dry etching techniques capable of obtaining a sufficiently high selection ratio between a layer to be etched and an underlying etching stopper film.
According to one aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: a step of covering a surface of an insulating film made of silicon-containing insulating material with a mask pattern, the insulating film being formed on a surface of a semiconductor substrate; and a step of dry-etching the insulating film by using the mask pattern as a mask and etching gas which contains C
4
F
8
gas and C
x
F
y
gas (wherein x and y are an integer and satisfy x≧5 and y≦(2x−1).
An etching selection ratio of the insulating film to the etching stopper film under the insulating film can be raised by using the etching gas which contains C
4
F
8
gas and C
x
F
y
gas (wherein x and y are an integer and satisfy x≧5 and y≦(2x−1).
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: a step of preparing a semiconductor substrate having a metal wiring whose upper surface is exposed on a surface of the semiconductor substrate; a step of forming an etching stopper film made of a first insulating material on the surface of the semiconductor substrate; a step of depositing an insulating film on the etching stopper film, the insulating film being made of a second insulating material which contains Si and has an etching resistance different from the etching stopper film; a step of covering a surface of the insulating film with a resist pattern having an opening superposed upon the metal wiring; a step of dry-etching the insulating film by using the mask pattern as a mask and etching gas which contains C
4
F
8
gas and C
x
F
y
gas (wherein x and y are an integer and satisfy x≧5 and y≦(2x−1), to form a recess and expose the etching stopper film on a bottom of the recess; a step of removing the resist pattern under a condition that the metal wiring is covered with the etching stopper film; a step of removing the etching stopper film exposed at the dry-etching step; and a step of burying conductive material in the recess etched by the dry-etching step to form a conductive member connected to the metal wiring, wherein an etching rate of the first insulating material is slower than an etching rate of the second insulating material when the dry-etching step is performed by the
Arent & Fox PLLC
Fujitsu Limited
Vinh Lan
LandOfFree
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