Mantissa processing circuit of floating point arithmetic apparat

Details Mantissa processing circuit of floating point arithmetic apparat Mantissa processing circuit of floating point arithmetic apparat

1991-12-27

1993-04-06

Mai, Tan V.

Boots, shoes, and leggings

G06F 738

Patent

active

052009165

ABSTRACT:
A mantissa processing circuit of a floating point arithmetic apparatus defines an arithmetic unit 11, a rounding adder 12, a postshift-count-encode circuit (PSCE circuit) 13, and a postshift circuit 14. The arithmetic unit 11 outputs as a first intermediate result (intermediate sum) R1 the results of addition and subtraction on preshifted mantissa data ma and mb. The rounding adder 12 outputs as a second intermediate result (rounding result) R2 the result of rounding addition for the intermediate sum R1. The PSCE circuit 13 outputs data on postshift to be applied to the rounding result R2. The postshift circuit 14 actually shifts the rounding result R2 to the right or left for normalization. The PSCE circuit 13 includes a shifting part 15 and a shift correcting part 16. The shifting part 15 specifies the contents of postshift according to the position of the first non-zero value bit in the intermediate sum R1. The shift correcting part 16 corrects the quantity of postshift when it is expected that the position of the first non-zero value bit is moved for a carry at the time of rounding addition. The rounding adder 12 and the PSCE circuit 13 execute processing in parallel, so that there can be enhanced the processing speeds of the rounding and normalization for the results of addition and subtraction on the mantissa data ma and mb.

REFERENCES:
patent: 4644490 (1987-02-01), Kobayashi et al.
patent: 4926369 (1990-05-01), Hokenek et al.
patent: 5063530 (1991-11-01), Ishikawa
patent: 5075882 (1991-12-01), Sakai et al.
Kaneko et al., "A VLSI RISC with 20-MFLOPS Peak, 64-bit Floating-Point Unit", IEEE Journal of Solid-State Circuits, vol. 24, No. 5, Oct. 1989, pp. 1331-1340.

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