Manchester carry adder circuit

Details Manchester carry adder circuit Manchester carry adder circuit

1988-06-15

1990-02-06

Harkcom, Gary V.

Boots, shoes, and leggings

364786, G06F 750

Patent

active

048993050

ABSTRACT:
A 16-bit adder architecture configured uniquely as two 8-bit adders. The first 8-bit adder uses a static technique to perform addition of the least significant bits and a dynamic technique to perform addition on the remaining bits. The second 8-bit adder uses a static technique to perform addition of the most significant bits and a dynamic technique to perform addition on the remaining bits. The two 8-bit adders are combined at the most significant bit of the first adder and the least significant bit of the second adder using the carry out of the first adder and the carry in of the second adder. A static logic gate is used to logically combine and correctly time the combination of the two 8-bit adders into a single, high-speed 16-bit adder.

REFERENCES:
patent: 4052604 (1977-10-01), Maitland et al.
patent: 4523292 (1985-06-01), Armer
patent: 4564921 (1986-01-01), Suganuma
patent: 4651296 (1987-03-01), Koike
patent: 4707800 (1987-11-01), Montrone et al.
patent: 4807176 (1989-02-01), Yamada et al.

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