Managing load and store operations using a storage...

Details Managing load and store operations using a storage... Managing load and store operations using a storage...

2005-08-30

2005-08-30

Chan, Eddie (Department: 2183)

Electrical computers and digital processing systems: processing

Dynamic instruction dependency checking, monitoring or...

Reexamination Certificate

active

06938148

ABSTRACT:
A Storage Reference Buffer (SRB) designed as an autonomous unit for all Store operations that transfer data from the execution unit of a processor to the memory hierarchy and Load operations that transfer data from the memory hierarchy to the execution unit of the processor. The SRB partitions up the Load and Store operations into several smaller operations in order to perform them in parallel with other Load and Store requests. System elements are included to determine unambiguously which of these Load and Store operations may be performed without waiting for prior operations to be completed. The SRB also includes system elements to detect whether requests may be satisfied by existing entries in the SRB without having to access the cache. The SRB is operated as a content addressable memory. Load request are simultaneously launched to cache and to the SRB with the Cache request being canceled if the Load request may be satisfied by an SRB entry.

REFERENCES:
patent: 5539892 (1996-07-01), Reininger et al.
patent: 5761712 (1998-06-01), Tran et al.
patent: 5764946 (1998-06-01), Tran et al.
patent: 5765035 (1998-06-01), Tran
patent: 5802588 (1998-09-01), Ramagopal et al.
patent: 5835962 (1998-11-01), Chang et al.
patent: 5848287 (1998-12-01), Tran et al.
patent: 6009516 (1999-12-01), Steiss et al.
patent: 6473832 (2002-10-01), Ramagopal et al.
InstantWeb. “Online Computing Dictionary.” Search terms: cache and register http://www.instantweb.com/foldoc.cgi?computer+dictionary.
Rosenberg, Jerry M. “Dictionary of Computers, Information Processing & Telecommunications”. Second Edition. New York: John Wiley & Sons, ©1987. p. 370.
Short, Kenneth L. “Microprocessors and Programmed Logic”. Englewood Cliffs, NJ: Prentice-Hall, Inc., ©1981. pp. 12-13 and 72-76.
Diefendorff, Keith. “PC Processor Microarchitecture,”Microprocessor Report, vol. 13, No. 9; via Internet at http://www.chipanalyst.com/x86/microarchitecture/index.html, pp. 1-16.
Brehob et al. “Beyond RISC-The Post-RISC Architecture,”IEEE Micro, Mar. 1996, via Internet at http://www.cs.msu.edu/˜crs/cps920/, pp. 1-19.
Gerritsen, Armin. “Out of Order Execution,” via Internet at http://cpusite.examedia.nl/docs/ooo.html, pp. 1-8.
Silc et al. “Asynchrony in Parallel Computing: From Dataflow to Multithreading,”Parallel and Distributed Computing Practices, vol. 1, No. 1, Mar. 1998; via Internet at http://www-csd.ijs.si/silc/pdcp.html, pp. 1-39.

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