Managing high speed slow access channel to slow speed cyclic sys

Details Managing high speed slow access channel to slow speed cyclic sys Managing high speed slow access channel to slow speed cyclic sys

1990-08-31

1992-09-08

Bowler, Alyssa H.

Boots, shoes, and leggings

395725, 395325, 364DIG1, G06F 1300, G06F 1312

Patent

active

051465760

ABSTRACT:
A cached DASD controller is illustrated which is attached to a high speed serial channel, such as an optical fiber channel. The data rate of the serial channel is much greater than the data rate of a DASD connected to the controller. The serial channel has a relatively long propagation time such that synchronous operations between the host processor 10 and the DASD cannot be efficiently performed. Operation of a data transfer, whether read or write between the host processor 10 and the DASD is monitored. Whenever reading a copy of the track contents stored in cache or the DASD reaches either an index mark, a break point from a roll mode operation or certain write operations occur resulting in predetermined data being stored in cache, then a GOCACHE flag is set in a control portion of the controller. The device operations are then momentarily idled while cache to host processor data transfer operations are enabled.

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patent: 4882642 (1989-11-01), Tayler et al.
patent: 4912630 (1990-03-01), Cochcroft, Jr.
patent: 4947319 (1990-08-01), Bozman
patent: 4956803 (1990-09-01), Tayler et al.

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