Managing external memory updates for fault detection in...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Commitment control or register bypass

Reexamination Certificate

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Reexamination Certificate

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07444497

ABSTRACT:
A multithreaded architecture is disclosed for managing external memory updates for fault detection in redundant multithreading systems using speculative memory support. In particular, a method provides input replication of load values on a SRT processor by using speculative memory support to isolate redundant threads form external updates. This method thus avoids the need for dedicated structures to provide input replication.

REFERENCES:
patent: 5415835 (1995-05-01), Brueck
patent: 6304318 (2001-10-01), Matsumoto
patent: 6625749 (2003-09-01), Quach
patent: 2002/0023202 (2002-02-01), Mukherjee
patent: 0915384 (1999-12-01), None
“Transient-Fault Recovery Using Simultaneous Multithreading”; Vijaykumar et al.; IEEE; 2002.
“Slipstream Processors: Improving both Performance and Fault Tolerance”; Sundaramoorthy et al.; ACM; 2000.
“Transient-Fault Recovery for Chip Multiprocessors”; Gomaa et al.; IEEE; 2003.
European Patent Office, International Search Report and Written Opinion for International Patent Application No. PCT/US2004/043649, 10 pages, Mar. 24, 2006.

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