Boots – shoes – and leggings
Patent
1982-12-17
1986-07-22
Thomas, James D.
Boots, shoes, and leggings
G06F 1210
Patent
active
046023283
ABSTRACT:
A system for the management of the physical memory of a processor which utilizes a base register which is loaded, for each virtual address of the memory, by a base address of a discriptive register corresponding to a task to be performed by the processor. This system utilizes a descriptive register table, an adder receiving the binary value of the base address of the first descriptive register, and the binary value of the index corresponding to the first register. The outputs of the adder address one of the inputs of the descriptive register table, thus selecting a segment descriptive register corresponding to the task to be performed. Each of the descriptive registers of the table contains control bits sent to the processor which makes it possible for the processor to check whether, for the segment to which the processor must have access, the processor must operate in the local or overall mode and whether the processor must process an input-output operation or an access to the memory.
REFERENCES:
patent: 4279014 (1981-07-01), Cassonnet
patent: 4300192 (1981-11-01), Couleur
patent: 4356549 (1982-10-01), Chueh
patent: 4376297 (1983-03-01), Anderson
The Journal "Computer", vol. 10, No. 5, May 1977, Longbeach, U.S.A.
"IBM Technical Disclosure Bulletin", vol. 18, No. 1, Jun. 1979.
Finger Ulrich
Ligneres Pierre
O'Donnell Ciaran
Institut National de Recherche en Informatique et en Automatique
L'Etat Francais represente par le Ministre des P.T.T. (Centre Na
Munteanu-Ramnic Florin
Thomas James D.
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