Management of channel buffer in video decoders

Television – Bandwidth reduction system – Format type

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348715, H04N 5907

Patent

active

053980727

ABSTRACT:
A novel channel buffer management scheme for a video decoder minimizes the amount of memory allocated to buffer a video bitstream received from a transmission channel. A channel buffer accumulates picture data encoded in a video bitstream received from a fixed rate channel. Picture data is read out of the channel buffer by a video decoder immediately after a predetermined or expected amount of bitstream data is received by the channel buffer. Picture decoding, reconstructing, and displaying operations are synchronized to permit the transfer of picture data from the channel buffer to the decoder whenever all of the data bits comprising a picture are received in the channel buffer. A microcontroller monitors and regulates the operation of the novel channel buffer management scheme to avoid overflow or underflow of bitstream data in the channel buffer. In accordance with one aspect of the present invention, a display controller and picture reconstruction means are fabricated as an monolithic integrated circuit device.

REFERENCES:
patent: 4785349 (1988-11-01), Keith et al.
patent: 5019906 (1991-05-01), Wesolowski
patent: 5212549 (1993-05-01), Ng et al.
patent: 5220425 (1993-06-01), Enari et al.

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