Electrical computers and digital processing systems: multicomput – Computer-to-computer data routing – Least weight routing
Reexamination Certificate
1998-04-30
2003-09-23
Courtenay, III, St. John (Department: 2126)
Electrical computers and digital processing systems: multicomput
Computer-to-computer data routing
Least weight routing
C711S173000
Reexamination Certificate
active
06625638
ABSTRACT:
TECHNICAL FIELD
This invention relates, in general, to logically partitioned computer systems and, in particular, to a logical partition that uses dedicated logical processors of one processor type and shared logical processors of another processor type to service requests.
BACKGROUND ART
Many computer hardware machines conforming to the International Business Machines Corporation S/390® architecture, as described, for example, in the IBM publication
Enterprise Systems Architecture
/390
Principles of Operation
, SA22-7201-04, June 1997, hereby incorporated herein by reference in its entirety, operate in what is known as logically partitioned (LPAR) mode. Logically partitioned computer systems are well known in the art and are described in Guyette et al., U.S. Pat. No. 4,564,903, entitled “Partitioned Multiprocessor Programming System”, issued on Jan. 14, 1986; Bean et al., U.S. Pat. No. 4,843,541) entitled “Logical Resource Partitioning Of A Data Processing System”, issued on Jun. 27, 1989; and Kubala, U.S. Pat. No. 5,564,040, entitled “Method And Apparatus For Providing A Server Function In A Logically Partitioned Hardware Machine”, issued on Oct. 8, 1996, each of which is hereby incorporated herein by reference in its entirety.
Commercial embodiments of logically partitioned systems include IBM S/390 processors with the Processor Resource/Systems Manager™ (PR/SM™) feature and described, for example, in the IBM publication
Processor Resource/Systems Manager Planning Guide
, GA22-7236-02, October 1997, hereby incorporated herein by reference in its entirety.
Logical partitioning allows the establishment of a plurality of system images within a single physical machine, or central processor complex (CPC). Each system image is capable of operating as if it were a separate computer system. That is, each logical partition can be independently reset, initially loaded with an operating system that may be different for each logical partition, and operate with different software programs using different input/output (I/O) devices. Logical partitioning is in common use today because it provides its users with flexibility to change the number of logical partitions in use and the amount of physical system resources assigned to each partition, in some cases, while the entire central processor complex continues to operate.
A recent addition to the IBM S/390 architecture, usually operating in a logically partitioned environment, is the IBM Parallel Sysplex™ configuration, comprising two or more systems interconnected via a coupling facility to form what is known as a “sysplex” (for “system complex”). A sysplex configuration may have more than one coupling facility, for example, a backup coupling facility set to take over if a primary coupling facility fails. Each system that is a member of a sysplex may be either a separate hardware machine or a separate logical partition of a particular hardware machine. In a similar manner, each coupling facility in the sysplex may be either a separate hardware machine or a separate logical partition of a particular hardware machine. Each S/390 coupling facility, whether a separate hardware machine or a separate logical partition of a particular hardware machine, is implemented by microcode known as coupling facility control code (CFCC).
In the S/390 Parallel Sysplex Architecture, a system issues a request to a coupling facility using a Send Message (SMSG) instruction. This instruction is executed by a central processor (CP) of the machine on which the system resides; this CP may be a logical CP, if the system resides in a logical partition. The executing CP causes a message command block (MCB) to be sent along a message path to the coupling facility and receives back a message response block (MRB) containing the results of the request. Message communication and other aspects of the operation of an S/390 coupling facility are described in such references as Elko et al., U.S. Pat. No. 5,561,809, entitled “In A Multiprocessing System Having A Coupling Facility, Communicating Messages Between The Processors And The Coupling Facility In Either A Synchronous Operation Or An A synchronous Operation”, issued on Oct. 1, 1996; Elko et al., U.S. Pat. No. 5 706,432, entitled “Mechanism For Receiving Messages At A Coupling Facility”, issued on Jan. 6, 1998; and the patents and applications referred to therein, all of which are hereby incorporated herein by reference in their entirety.
SMSG instructions may be executed either synchronously or asynchronously. When executed asynchronously, the SMSG instruction is completed as soon as the request in the form of an MCB is sent off to the target coupling facility. When executed synchronously, on the other hand, the SMSG instruction is not completed until a response in the form of an MRB is received back from the target facility. The handling of synchronous and asynchronous requests in an S/390 Parallel Sysplex environment is described further in the co-pending application of applicant J. P. Kubala et, al., Ser. No. 08/903,285, now U.S. Pat. No. 5,923,890 filed Jul. 30, 1997, hereby incorporated herein by reference in its entirety.
A particular hardware machine or central processing complex has a limited amount of capacity. That is, it can only support a fixed number of central processors. These processors can be used for user workloads, such as OS/390 workloads, or for coupling facility functions.
The offering of a coupling facility partition on a machine typically reduces the number of processors available to run user workloads or to be activated as spares, in the event of a processor failure. This is due to the fact that in order to keep software licensing costs down, the processors configured for the coupling facility logical partition are usually dedicated to run only coupling facility microcode. Since these processors do not have user software loaded thereon, the user capacity of the machine is not increased, and neither is the software licensing cost, which is based on user capacity.
The dedicated coupling facility processors, however, only provide a fixed amount of processing capability for the coupling facility partition. Thus, there is a concern that the fixed CPU capacity of those processors may not be sufficient to handle peak workloads of the coupling facility running within the logical partition. In current configurations, this workload peak can be from a temporary spike in utilization due to, for instance, end of the month workloads, or due to a failure of another primary coupling facility. This capacity issue becomes an even larger concern with the current move towards integrating this technology more tightly into the parallel sysplex platform.
Based on the foregoing, a need exists for a capability that provides additional capacity to a coupling facility logical partition, when needed, without requiring another dedicated processor. A further need exists for a capability that can provide the above without requiring additional machines to service user workloads, thus, increasing the user's costs. A yet further need exists for a capability that maximizes effective use of a customer's hardware, while minimizing both hardware and software costs to the user, and providing dynamic rebalancing of resources to increase total system availability.
SUMMARY OF THE INVENTION
The shortcomings of the prior art are overcome and additional advantages are provided through the provision of a method of managing logical partitions. The method includes, for instance, using one or more dedicated logical processors to service one or more requests forwarded to a logical partition of a computer environment; and utilizing one or more shared logical processors to service one or more requests forwarded to the logical partition. The one or more dedicated logical processors includes one or more special purpose processors, and the one or more shared logical processors includes one or more general purpose processors.
In one embodiment, the one or more special purpose processors is incapable of running one or more types of softwa
Kubala Jeffrey Paul
Nagy John Charles
Nick Jeffrey Mark
Siegel Ira Glenn
Courtenay III St. John
Cutter, Esq. Lawrence D.
Schiller, Esq. Blanche E.
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