Malicious fault list generation method

Details Malicious fault list generation method Malicious fault list generation method

1995-06-06

1996-10-01

Beausoliel, Jr., Robert W.

G06F 1100

Patent

active

055617620

ABSTRACT:
A method for selecting and responding to a malicious fault in a reconfigurable electronic apparatus that can perform multiple tasks, and that has fault processing for counteracting a class of faults which can generally cause the apparatus to fail during the execution of a preselected task if the fault processor is unavailable and to which class the malicious fault can belong. The reconfigurable electronic apparatus can be a fault processing system, which can be an interlocking control circuit, or a combinational circuit. The method includes constructing an information flow representation of at least a portion of the apparatus executing the preselected task of interest; applying a preselected fault representation to the information flow representation and producing multiple input error conditions corresponding to at least one preselected output condition, the preselected fault representation including recursive reverse implication and, where reconvergent fanout occurs, a forward consistency check; selecting from the aforementioned multiple input error conditions at least one fault condition corresponding to the class of faults; injecting the at least one fault condition into the information flow representation and producing a malicious fault condition representative of said malicious fault; and modifying the apparatus responsive to the malicious fault condition, thereby counteracting the malicious fault. The malicious fault can belong to the class of faults occurring during execution of the preselected task by the apparatus and causing the apparatus to fail during such execution.

REFERENCES:
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patent: 4996688 (1991-02-01), Byers et al.
patent: 5046068 (1991-09-01), Kubo et al.
patent: 5193178 (1993-03-01), Chillarege et al.
patent: 5243607 (1993-09-01), Masson et al.

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