Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip
Reexamination Certificate
2001-04-06
2002-08-20
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Chip mounted on chip
C257S676000, C438S107000
Reexamination Certificate
active
06437449
ABSTRACT:
BACKGROUND
1. Technical Field
This invention pertains to semiconductor device packaging in general, and in particular, to packaging semiconductor device having stacked dies with electrically biased back surfaces.
2. Related Art
A demand for electronic devices that are smaller, lighter, and yet more functional has resulted in a concomitant demand for semiconductor packages that have smaller outlines and mounting footprints, yet which are capable of increased component packaging densities. One approach to satisfying this demand has been the development of techniques for stacking the semiconductor dies, or “chips,” contained in the package on top of one another. Examples of die-stacking techniques may be found in, for example, U.S. Pat. Nos. 5,323,060 and 5,721,452 to R. Fogel, et al.; U.S. Pat. No. 5,815,372 to W. N. Gallas; U.S. Pat. No. 5,898,220 and Re. 36,613 to M. B. Ball; and, Japanese Patent Disclosures 62-126661, 4-56262, 63-128736, and 10-256470.
Another demand has been for devices in which the back surfaces of the respective dies can be biased to an electrical potential, e.g., ground (“V
ss
”). A prior art approach to meeting this demand may be found in, e.g., U.S. Pat. No. 6,005,778 to R. K. Speilberger, et al. In this device, a substrate, e.g., a ceramic laminate, has an electrically conductive die-mounting pad surrounded by a plurality of conductive pads or leads. A first semiconductor die is mounted on the die-mounting pad such that its back surface is in electrical connection with the pad, i.e., with an electrically conductive adhesive.
An electrically conductive spacer is mounted on the front surface of the first die such that it is electrically isolated therefrom. The spacer is sized to fit inside wire bonding pads on the front surface of the first die, and has a plated, peripheral wire bonding “tier,” or step, formed therein, so that both the step and the bonding pads are frontally exposed for wire bonding. The die-mounting pad and the peripheral step in the spacer are respectively wire bonded to a specific lead of the substrate.
A second semiconductor die is mounted with its back surface on and in electrical connection with the spacer, i.e., with an electrically conductive adhesive. By connecting the specific lead to an electrical potential, e.g., V
ss
, both the die-mounting pad and the spacer, and hence, the respective back surfaces the two dies are biased to that potential.
While the prior art device provides one approach to the demand for a device having stacked dies with biased back surfaces, the electrically conductive spacer, with its plated, peripheral wire bonding step, increases the complexity and thickness of the device, resulting in a thicker, more costly device. A thinner, less costly solution is therefore desirable.
SUMMARY
This invention provides a semiconductor device having multiple, stacked dies of the same or different sizes in which the back surfaces of each die can be biased to the same or different electrical potentials, in a package that is thinner and simpler to construct than those afforded by the prior art.
In one advantageous embodiment, the novel device includes a substrate, e.g., a lead frame, that includes an electrically conductive die-mounting pad and a plurality of electrically conductive leads arrayed around the pad. A first semiconductor die having a front surface with a plurality of wire bonding pads arrayed around a periphery thereof, and an opposite back surface, is mounted on the die-mounting pad such that the back surface of the die is in electrical connection with the pad.
A spacer of a uniform thickness is provided. The spacer may be of an electrically conductive or a dielectric material, and has a front surface, an opposite back surface, and an outer periphery that is smaller than an inner periphery of the wire bonding pads on the first die. The spacer is mounted on the front surface of the first die such that the spacer is located inside the inner periphery of the wire bonding pads thereon and is electrically isolated therefrom.
In one possible embodiment, at least one electrically conductive wire is bonded at a first end to at least a first lead of the substrate, the die-mounting pad, or a first wire bonding pad on the first die, and at a second end to the front surface of the spacer. In another possible embodiment, the second end of the wire is bonded to a second lead of the substrate, to the die-mounting pad, or to a second wire bonding pad on the first die, such that at least a portion of the wire between the two ends extends across at least a portion of the front surface of the spacer.
A second semiconductor die having opposite front and back surfaces is mounted with its back surface on the front surface of the spacer with layer of an electrically conductive material such that the portion of the conductive wire spanning the spacer is embedded in the conductive layer. This mounting electrically connects the back surface of the second die to the conductive wire, enables the thickness of the conductive adhesive to be reduced to the height of the wire bonds, or to the thickness of the wire itself, and eliminates the need for an electrically conductive spacer having a wire bonding “step” thereon, thereby resulting in a device package that is thinner, simpler, and less expensive to make than prior art packages.
The above and many other features and advantages of this invention will become apparent from a consideration of the following detailed description of the various embodiments thereof, particularly if such consideration is made in conjunction with the appended drawings.
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patent: 6005778 (1999-12-01), Spielberger et al.
patent: RE36613 (2000-03-01), Ball
patent: 6057598 (2000-03-01), Payne et al.
patent: 6072243 (2000-06-01), Nakanishi
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patent: 62-126661 (1987-06-01), None
patent: 63128736 (1988-06-01), None
patent: 4-56262 (1992-02-01), None
patent: 10-256470 (1998-09-01), None
Amkor Technology Inc.
Costanzo Patricia M.
Skjerven Morrill LLP
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