Making LSI devices with double level polysilicon structures

Details Making LSI devices with double level polysilicon structures Making LSI devices with double level polysilicon structures

1981-10-09

1984-07-10

Ozaki, G.

Metal working

Method of mechanical manufacture

Assembling or joining

29577C, 29576B, 29578, H01L 21225, H01L 21265, H01L 2128

Patent

active

044584067

ABSTRACT:
The high resistance of diffused electrical interconnection lines used for ground return paths in MOS field effect transistor (MOSFET) arrays limits their size and performance. Advantage is taken of the extra interconnection level available from conventional double-layer-polycrystalline silicon (polysilicon) processes to distribute ground potential to arrays, by means of a polycrystalline grid with direct contact to diffused electrodes therein, thus greatly reducing the deleterious effects of ground resistance. The proposed ground grid is integrated into the structure of a MOSFET ROM using a typical double polysilicon process. The first polysilicon level provides the conductive medium for said ground grid and the diffusing doping impurities that form contiguous source electrodes for the array MOSFETs. Gate electrodes thereof and word lines are formed out of the second polysilicon level. Drain electrodes are diffused and contacted by metallized output lines.

REFERENCES:
patent: 3914855 (1975-10-01), Cheney et al.
patent: 3958323 (1976-05-01), De La Moneda
patent: 4056810 (1977-11-01), Hart et al.
patent: 4075045 (1978-02-01), Rideout
patent: 4207585 (1980-06-01), Rao
patent: 4240195 (1980-12-01), Clemens et al.
patent: 4380863 (1983-04-01), Rao

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