Making integrated circuit transistor having drain junction offse

Details Making integrated circuit transistor having drain junction offse Making integrated circuit transistor having drain junction offse

1993-08-31

1994-09-06

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 41, H01L 21336

Patent

active

053447905

ABSTRACT:
A method for fabricating an integrated circuit transistor begins with forming a gate electrode over an insulating layer grown on a conductive layer. Sidewall spacers are formed alongside vertical edges of the gate electrode and a mask is applied to a drain region. A relatively fast-diffusing dopant is then implanted into a source region in the conductive layer. Thereafter, the mask is removed and the drain region is implanted with a relatively slow-diffusing dopant. Finally, the conductive layer is annealed, causing the relatively fast-diffusing dopant to diffuse beneath the source sidewall spacer to a location approximately beneath the vertical edge of the source side of the gate electrode, and causing the relatively slow-diffusing dopant to extend beneath the drain sidewall spacer a lesser distance, so that the drain junction is laterally spaced from underneath the gate electrode. Due to the difference in diffusion rates between the relatively slow-diffusing dopant and the relatively fast-diffusing dopant, a transistor having a drain junction offset is formed.

REFERENCES:
patent: 4852062 (1989-07-01), Baker et al.
patent: 5063172 (1991-11-01), Manley
patent: 5108935 (1992-04-01), Rodder
patent: 5210044 (1993-05-01), Yoshikawa
patent: 5258319 (1993-11-01), Inuishi et al.

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