Making epitaxial semiconductor device

Details Making epitaxial semiconductor device Making epitaxial semiconductor device

1998-09-28

2001-05-08

Smith, Matthew (Department: 2825)

Metal treatment

Barrier layer stock material, p-n type

Having at least three contiguous layers of semiconductive...

C438S048000, C438S492000, C438S495000, C438S496000, C438S497000, C438S500000, C438S501000, C438S503000

Reexamination Certificate

active

06228181

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention is the most applicable to the solar cell(s) which being formed by the semiconductor layers having the different conductive type as well as the different specific resistance by making a structure of catching the incoming light to the P-N junction portion which being formalized by either in flat form or in uneven form, and also by making the wafer which being formed by an epitaxial growth a cheaper fabrication cost.
2. Description of the Related Art
The semiconductor wafer on which many devices as transistors ICs and others being formed should be highly and purely controlled in wafer itself. It has usually 100 &OHgr;cm through several hundreds &OHgr;cm in his specific resistance (Semiconductor Grade Silicon-SG—Si).
It has also the necessity of mirror polishing on its semiconductor plate which being formed in high pure crystal level when it is formed the transistor(s) and other active circuits in it, then, a semiconductor circuits are usually formed within 5 &mgr;m from its mirror surface by either a diffusion method or an epitaxial method when an epitaxial growth can be made by P or N type semiconductor layer within several &mgr;m in its thickness.
Followings are the reasons why a mirror polishing being necessity on the semiconductor wafer surface.
(1) If the distance from the P-N junction face to the bottom of the diffusion circuit(s) being not kept in constant, the total junction capacities which being consisting of the P-N junction depletiation layer's capacity and the diffusion portion's capacity, and the circuit fixed time constants shall be changed due to the impurity distribution's non-uniformity at the P-N junction portion. this can not be enabled a hopeful circuit construction.
(2) A circuit can not work as well as of scheduled due to non constant value in the capacitance and in the resistance because there are existing of unwilling uneven on P-N junction portion.
Due to the above two defects, this will not be impracticable because the electricity which being generated at the P-N junction portion shall be changed to a heat in its wafer instead of giving it to the outside circuit.
According to the above reasons, there should be keep constant the scope of impurity contents (N type or P type impurity contents) as well as the oxygen contents in the semiconductor wafer.
For example, in the pulling upped crystal by Czochoralski Method (CZ- method), each about 15% of its head portion and bottom portion of the crystal body shall be removed for only using an uniformed impurity contents parts.
Then the above remaining 15% portions are usually used as for solar cell(s), for reproduction crystal or for high power transistors.
Further, The portion of using as a semiconductor wafer in the pulled up crystal shall be sliced by a diamond cutter or a wire saw to have been 0.5-1.0 mm in their wafer thickness.
The essential problem in this respect is that each wafer's production cost should be extremely high like of the diamond, because of the utility ratio of this high purity semiconductor crystal being about 50% of the total body due to produce the semiconductor wafer by sliced in a preliminary thickness upon preliminary removing of the head and tail portions in which a rather higher impurity contents being to be included.
There is also a defect of having a trend of worse along the outside toward in its impurity contents ratio while its diameter shall be enlarged by and by. This phenomenon may bring some change in a circuit constant value and there have some limitation to the crystal diameter at the fabrication of IC wafer.
There is also a fear of falling down of the pull-upped crystal which having 100 Kg or more in its weight. Therefore, there is a limitation to pull-up the crystal which being usually less than 100 Kg in its weight.
As the fourth essential point, the wafer production cost should be much higher as well, due to the more awkward production process, upon the necessity of the wafer surface mirror polishing for keeping the wafer flatness by &mgr;m order.
This means that the result of making the mirror polishing on the wafer surface leads to be necessary attached the inspection process of examining whether the mirror polished surface shall be in the scope of the allowance in order, upon the necessity of the expensive wafer polishing machine.
But, it is an only area to several &mgr;m from the surface of the semiconductor wafer that the necessity portion for making a devices as transistor circuits and others in the wafer as mentioned in the above (1) and (2). There is not so necessary portions in other portions which being lower than the portion from above several &mgr;m in its depth to the bottom of the wafer for making a devices as transistor circuits, but it is only used for supporting the upper above active portions.
This means that there is no necessity of considering for using such high cost as well as high purity semiconductor wafer until such supporting portions. On the other hand, there is an enough potion for manufacturing a solar cell(s) for considering a high impurity area in only several &mgr;m in wafer's thickness, and other portions than the above should not be necessary to consider its purification at all.
As other essential points for manufacturing the solar cell(s) by a semiconductor wafer, there is the necessity of more higher Light to Electricity transfer effect in its solar cell(s).
Following two points are essentials for obtain it;
a) Effective enlargement of the P-N junction layer.
b) Light transparent amounts at the P-N junction portion should be grown.
SUMMARY OF THE INVENTION
The first object of this invention is of making up the substantial Light-Electricity transfer effect of the solar cell(s) while the solar cell(s) production costs shall be kept at lower level as possible due to no making any critical mirror polishing on the surface of its semiconductor wafer, and making up-grade of the yield of the cell(s) while such semiconductor wafer standards as in flat level degree, in impurity distribution degree, in crystal defects degree and etc., as well as due to enlarge the P-N junction portion by making the fine uneven at its portion,
The second object of this invention is of making up the substantial Light-Electricity transfer effect of the solar cell(s) for making the incoming light's transparent numbers growth at the portion of P-N junction surface at which Light-Electricity transfer being made by fabricating the light reflection surface at both outsides of such P-N junction face, while the junction face between the semiconductor plate portion (for example PH) and the CVD layer (for example P+) at the semiconductor basic plate shall also working as the light reflector due to different of the resistances at both sides.
Then the light reflector is covered on the upper N(or P)layer at the P-N junction portion.
This is to say that as shown in
FIG. 3
, the sun light shall penetrate the upper light reflection layer, and further penetrate the P-N junction portion at about 80% of it while 20% of the light energy shall be transferred to the electricity at the portion of said P-N junction portion. Then, said penetrated 80% light energy shall attain the second light reflection surface. At the reflection surface around 40% of said penetrated 80% light energy shall be reflected. Then it penetrate through such P-N junction portion again, meanwhile 20% of such penetrating light energy (around 6% or so of the first incoming light energy) shall be transferred into the electricity. Further penetrating light energy shall attain the upper reflection layer, then, reflect again toward to said P-N junction.
At this time, generally speaking, P++:0.01 &OHgr;cm or less in the specific resistance, and P+: 0.02-5.00 &OHgr;cm in the specific resistance.
As mentioning above, there is designed in this structure of the incoming light shall penetrate through P-N junction portion with several times, the Light-Electricity transfer effect shall elevate to be 30% or s

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