Making chip size semiconductor packages

Details Making chip size semiconductor packages Making chip size semiconductor packages

2000-02-04

2002-01-15

Fahmy, Wael (Department: 2823)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Insulative housing or support

C438S127000, C438S108000, C257S723000, C257S778000

Reexamination Certificate

active

06338985

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor packaging in general, and in particular, to a method of making low cost, chip size semiconductor packages (“CSPs”).
2. Description of the Related Art
The recent trend in the electronics industry towards devices that are smaller and more densely packaged has resulted in a concomitant demand for semiconductor packages which are smaller and yet provide higher component mounting densities. One response to this demand has been the development of so-called ball grid array (“BGA”), land grid array (“LGA”), and lead-less chip carrier (“LCC”) packages that lack conventional leads, have a “footprint” that is the same size as the package, and are “chip size,” in that they have virtually the same length and width as those of the semiconductor die or “chip” packaged therein.
A near-chip-size, micro-BGA (“&mgr;BGA”) package developed by Tessera, Inc., is described in “Reliable BGAs Emerge In Micro Form,”
Electronic Engineering Times
p. 104, 111 (September 1994), T. H. DiStefano. In such packages, pads on the die are connected to metallizations on a flexible polyimide resin tape substrate by tape automated bonding (“TAB”) techniques. A compliant elastomeric layer, or “interposer,” is disposed between the die and the substrate, and is attached to the face of the die with a layer of a silicon rubber. The die, in turn, is bonded to a “thermal spreader” with a layer of adhesive, and the die and TAB bonds are overmolded with a flexible, silicone resin envelope.
The Mitsubishi Company of Tokyo, Japan, has also developed a chip size package (the “MCSP”) that uses a “flip chip” method of attaching a die to a substrate and reduces the number of different materials and material interfaces required in the package, as compared to the &mgr;BGA described above. While this reduction achieves a desirable increase in product reliability, the gain is offset somewhat by certain cost increases in the package resulting from the processes used in its fabrication, including forming interconnecting solder bumps on the substrate, rather than on the die, the use of “standoffs” to prevent collapse of the chip onto the substrate, the plating of connection pads on the die with an expensive under-bump metallization (“UBM”) such as gold, the use of a “hot gas” method of attachment of the die to the substrate, and the need to mold the bodies of the packages individually, rather than molding a large number of packages simultaneously, and in two separate operations, rather than in a single step.
A need therefore exists in the industry for a low cost, reliable, chip size semiconductor package that uses conventional CSP assembly processes, yet one which reduces the total number of materials and material interfaces in the package, as well as the number of process steps used in its fabrication. This need is particularly felt in the highly competitive, high-volume, memory chip field, where packaging costs and reliability can be determinative of profit or loss.
BRIEF SUMMARY OF THE INVENTION
The present invention provides a method for making low cost, chip size semiconductor packages that uses conventional packaging materials and processes, is well suited for making low cost memory packages, and results in packages with enhanced reliability.
One embodiment of a method in accordance with the present invention includes preparing a semiconductor die by forming solder bumps on the input/output pads of the die. An insulative substrate having a first surface with a pattern of metallizations formed thereon is also prepared. The metallizations comprise a plurality of pads corresponding to the pads on the die, a plurality of solder ball lands, and a plurality of traces connecting the pads to the lands. A second surface of the tape opposite the first surface has a plurality of openings formed through it at locations corresponding to the locations of the lands, so that the lands are exposed through the second surface of the tape by the openings. Of importance, the substrate has one or more vent openings formed through it in a central region thereof, and can be formed simultaneously with the land openings.
A solder mask is formed over the metallizations on the substrate. The mask includes apertures through which the pads on the substrate are exposed, as well as one or more vent openings corresponding to the vent openings in the substrate.
The die is placed on the masked substrate such that the die is located over the one or more vent openings in the solder mask and the substrate, and such that the solder bumps on the die contact the corresponding pads on the substrate through the apertures in the solder mask. The solder mask functions both conventionally and as a “standoff” for the die, and defines a narrow space between the first surface of the solder mask and an opposing first surface of the die. The die is electrically connected to the substrate using the “flip chip” connection method in which the solder bumps between corresponding pads on the die and the substrate are reflowed to form a bridge between the pads.
The substrate and the attached die are placed in the cavity of a mold. Molten plastic is forced into the cavity such that the plastic displaces the air in the cavity and forces it out of the cavity through the one or more vent openings in the substrate and solder mask, thereby forming a body of an insulative material on the first surface of the substrate that simultaneously overmolds the semiconductor die and underfills the space between the substrate and the die in a single step.
By using a single-sided substrate with a solder mask, reflowed eutectic solder balls formed on the die, a flip chip interconnection method, and a single-step package molding and underfilling process, the present invention utilizes only conventional fabrication methods, yet permits a reduction over the prior art in the total number of materials and material interfaces required in the package, and hence, an increase in its reliability. It also permits a reduction in the number, complexity and expense of the processes required by prior art packaging methods, such as forming metallizations on both sides of the substrate, connecting the metallizations with plated-through via holes, the use of standoffs and/or gold plating on the metallizations on the substrate, TAB or wire bonding of the die, hot gas attachment of the die, forming bumps on the substrate, and molding package bodies individually and/or in a two-step molding process involving separate underfilling and over-molding steps.


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