Majority logic circuit for digital error correction system

Details Majority logic circuit for digital error correction system Majority logic circuit for digital error correction system

1985-01-16

1987-04-21

Smith, Jerry

Excavating

307464, G06F 1110

Patent

active

046601996

DESCRIPTION:

BRIEF SUMMARY
TECHNICAL FIELD

This invention relates to the detection of a threshold value in an error correction circuit.


BACKGROUND ART

In a character and picture image information system such as videotex, teletext and the like, when a character multiplexing of a code system is carried out, it is proposed that the (272, 190) majority-logic decodable code is used to carry out the error correction.
The (272, 190) majority-logic decodable code represents that one data packet is formed of 272 bits, in which 190 bits are assigned to information bits and remaining 82 (=272-190) bits are assigned to error correction parity bits.
However, when the (272, 190) majority-logic decodable code is used, upon decoding, the parity check is carried out by parity check bits of 17 bits, A1 to A17. Thus, the majority logic circuit must identify whether the number of "1" bits in the 17 party check bits, A1 to A17, is less than 10 or not. As a result, the majority logic circuit must comprised logic circuits for all different combinations expressed as .sub.17 C.sub.10 mathematically, or 19448 different combinations, thus a great number of AND circuits and OR circuits being required.
Further, an IC on the market is generally two-input or four-input AND circuits and OR circuits and 17-input AND circuit and OR circuit are not available. Therefore, in practice, the majority logic circuit requires much more AND circuits and OR circuits and this is disadvantageous from a manufacturing cost and size or power consumption standpoint.
In addition, if the number of the AND circuits and the OR circuits used is increased, the processing speed of the majority logic circuit becomes low on the whole and this is not preferable in view of reliability.
For this reason, this invention is to provide a majority logic circuit of a very simple circuit arrangement.


DISCLOSURE OF INVENTION

In this invention, there are provided a plurality of memories in which predetermined data are stored, as well as a plurality of gates. Parity check bits are grouped into a plurality of groups in response to the bit number of the address of the memories. Of the grouped parity check bits, the parity check bits corresponding to the addresses of the memories are supplied to the addresses and the outputs of the memories are supplied to the gates so as to decode the parity check bits. A threshold value is identified on the basis of the outputs of the gates.
In consequence, according to this invention, it is possible to construct a majority logic circuit by several memories and several gate ICs.
Further, since a memory and gate IC on the market can be used as those of the majority logic circuit, the majority logic circuit can be made at low cost. Furthermore, since the majority logic circuit can be formed of several memories and several gate ICs, its space factor is excellent and the power consumption can be reduced. In addition, since the number of the circuit stages in the majority logic circuit is small, the processing speed thereof is high ahd the reliability thereof is satisfactory.


BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a circuit diagram showing an embodiment of a majority logic circuit according to this invention and FIG. 2 is a diagram useful for the explanation thereof.
Reference numerals 1 and 2 designate ROMs and reference numerals 301 to 315 and 4 designate gates.


BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 1 shows an embodiment of this invention. In FIG. 1, reference numerals 1 and 2 respectively designate 8 bit-256 bytes (256 addresses) ROMs. Data stored in the ROMs 1 and 2 are same to each other and the data stored at the respective addresses are as shown in FIG. 2.
When the address bits of the ROMs 1 and 2 are taken as AD7 to AD0 and the data bits thereof are taken as D7 to D0, if the number of the bits "1" in the address bits AD7 to AD0 is taken as N, N least significant bits (LSB) of the data bits D7 to D0 are set to "1". In other words, data DATA expressed as the address bits AD3, AD2 and AD0 are "1" at address 13, three less significant bits D2, D1 and

REFERENCES:
patent: 3784978 (1974-01-01), Zola
patent: 4309772 (1982-01-01), Kloker
patent: 4322848 (1982-03-01), Snyder
patent: 4404674 (1983-09-01), Rhodes
D. J. Costello, "Error Control Coding", pp. 184-200, .COPYRGT.1983.
G. C. Clark, "Error-Correction Coding for Digital Communications", pp. 143-148, .COPYRGT.6/1981.

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