Majority decision method and circuit wherein least possible flip

Details Majority decision method and circuit wherein least possible flip Majority decision method and circuit wherein least possible flip

1991-09-16

1993-08-10

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

371 36, 371 691, H03K 1923

Patent

active

052352200

ABSTRACT:
On determining an entire majority of five i-th received data bits which correspond to an i-th original data bit repeatedly received five times, first through I-th received data bits of a first received frame are stored in a main buffer (41) as first through I-th memorized data bits. A first partial majority is determined as regards two data bits, the i-th memorized data bit and an i-th received data bit of a second received frame. When the two data bits are and are not identical, first and second logic values are stored in an auxiliary buffer (42) as an i-th auxiliary data bit. Second and third partial majorities are successively determined by using the memorized and the auxiliary data bits. Likewise determined, a fourth partial majority gives the entire majority. When an original frame is repeatedly received more than five times, first through (N-1)-th counter buffers are substituted for the auxiliary buffer to memorize first through I-th memorized counts for use together with the memorized data bits in successively determining partial majorities of the type described.

REFERENCES:
patent: 4132975 (1979-01-01), Koike
patent: 4400811 (1983-08-01), Brown et al.
patent: 4404677 (1983-09-01), Grande et al.
patent: 4852105 (1989-06-01), Kurz
patent: 4959836 (1990-09-01), Berard et al.

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