Majority decision logic circuit

Details Majority decision logic circuit Majority decision logic circuit

1976-12-15

1978-05-23

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307211, 307215, H03K 1908, H03K 1942

Patent

active

040912930

ABSTRACT:
A majority decision logic circuit has an odd number of elementary input signal circuits connected in parallel with a power source, each of the elementary input signal circuits being composed of a pair of P- and N-channel MOS transistors, the drains of the MOS transistors being interconnected to form an output terminal at the connection point and the gates being interconnected to form an input terminal at the connection point, all the output terminals of the elementary input signal circuits being connected together to form the output terminal of the majority decision logic circuit. A majority decision logic circuit has, in addition to the odd number of elementary input signal circuits, a plurality of logic circuits having their output terminals respectively connected to the input terminal of the elementary input signal circuits. A majority decision logic circuit comprises the elementary input signal circuits, the logic circuits and switching circuits, whereby the majority of outputs of a selected odd number of input signal circuits is decided. The abovesaid circuits can be formed with MOS transistors only, and are easily fabricated as an integrated circuit.

REFERENCES:
patent: 3356858 (1967-12-01), Wanlass
patent: 3715603 (1973-02-01), Lerch
patent: 3737673 (1973-06-01), Suzuki
patent: 3896429 (1975-07-01), Moyer et al.
patent: 3900742 (1975-08-01), Hampel et al.
patent: 3925685 (1975-12-01), Suzuki
patent: 3945000 (1976-03-01), Suzuki et al.
Suzuki et al.,"Clocked CMOS Calculator Circuitry", IEEE JSSC, vol. SC-8, No. 6, pp. 462-469, 12/1973.
Freeman, "Complementary Voting Circuit", IBM Tech. Discl. Bull., vol. 16, No. 9, pp. 2902-2903, 2/1974.

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