Maintaining synchronism between a processor pipeline and subsyst

Details Maintaining synchronism between a processor pipeline and subsyst Maintaining synchronism between a processor pipeline and subsyst

1997-11-19

1999-10-19

Eng, David Y.

G06F 930, G06F 1100

Patent

active

059702419

ABSTRACT:
A data processing system on an integrated circuit 42 with microprocessor 1 and peripheral devices 60-61 is provided with an emulation unit 50 which allows debugging and emulation of integrated circuit 42 when connected to an external test system 51. Microprocessor 1 has in instruction execution pipeline which has several execution phases which involve fetch/decode units 10a-c and functional execution units 12, 14, 16 and 18. The pipeline of microprocessor 1 is unprotected so that memory access latency to data memory 22 and register file 20 can be utilized by system program code which is stored in instruction memory 23. Emulation unit 50 provides means for emulating the unprotected pipeline of microprocessor 1 and for rapidly uploading and downloading memories 22-23. Emulation unit 50 operates in a manner to prevent extraneous operations from occurring which could otherwise affect memories 22-23 or peripheral devices 60-61 during emulation.

REFERENCES:
patent: 4025771 (1977-05-01), Lynch et al.
patent: 4701921 (1987-10-01), Powell et al.
patent: 4760519 (1988-07-01), Papworth et al.
patent: 4783783 (1988-11-01), Nagai et al.
patent: 4860290 (1989-08-01), Daniels et al.
patent: 4916652 (1990-04-01), Schwarz et al.
patent: 5008807 (1991-04-01), Krueger et al.
patent: 5203003 (1993-04-01), Donner
patent: 5239633 (1993-08-01), Terayama et al.
patent: 5404473 (1995-04-01), Papworth et al.
patent: 5465334 (1995-11-01), Sato
patent: 5471626 (1995-11-01), Carnevale et al.
patent: 5535331 (1996-07-01), Swoboda et al.
patent: 5564028 (1996-10-01), Swoboda et al.
The Implementation and Application of Micro Rollback in Fault-Tolerant VLSI Systems, IEEE, 1988, pp. 234-239.
A Survey of Design for Testability Scan Techniques, VLSI Design, Dec. 1984, pp. 38-39, 42, 46, 48, 59-61.
TMX320C6201 Digital Signal Processor, Texas Instruments Product Preview, Jan. 1997, p. 1.
TMS320C62xx CPU and Instruction Set, Texas Instruments Product Preview, Jan. 1997, p. 1.

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