Maintaining data coherency between a central cache, an I/O cache

Details Maintaining data coherency between a central cache, an I/O cache Maintaining data coherency between a central cache, an I/O cache

1992-04-30

1993-09-21

Kulik, Paul V.

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364DIG1, 3642434, 36424341, 36424344, 3642435, 3642455, 3642456, 364246, 3642463, 3642423, 36424231, G06F 1208, G06F 1300

Patent

active

052476480

ABSTRACT:
An I/O write back cache memory and a data coherency method is provided to a computer system having a cache and a main memory. The data coherency method includes partitioning the main memory into memory segments, dynamically assigning and reassigning the ownership of the memory segments either to the cache memory or the I/O write back cache memory. The ownership of the memory segments controls the accessibility and cacheability of the memory segments for read and write cycles performed by the CPU and I/O devices. During reassignment, various data management actions are taken to ensure data coherency. As a result, the I/O devices can perform read and write cycles addressed against the cache and main memory in a manner that increases system performance with minimal increase in hardware and complexity cost.

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