Main storage validation means

Details Main storage validation means Main storage validation means

1980-08-11

1982-07-27

Atkinson, Charles E.

Boots, shoes, and leggings

371 10, 371 21, 371 38, G06F 1110, G11C 2900

Patent

active

043420842

ABSTRACT:
Method and means for validating any BSM in main storage while main storage remains available for normal system operation by all CPUs in the system. The system has plural sets of BSMs in which any set can be operationally fenced from system operation in order to validate any BSM in the fenced set, while the system normally operates with the unfenced set(s) of BSMs comprising main storage. Each BSM set has a BSM controller which is integrated with a hardware BSM tester. All cells in and the addressing circuits to any BSM can be tested by incrementing line addresses through the BSM while comparing a true pattern and then a complement pattern, and then decrementing line addresses through the BSM comparing the complement pattern and then the true pattern. The BSM testers use level sensitive scan design (LSSD) circuits in the BSM controller to serially communicate with a system service processor in response to commands from the service processor and interrupt signals from the BSM tester. A marker mask in each BSM tester permits BSM testing continuity after each interrupt signal. Between commands, the BSM tester can operate automatically and in parallel with the service processor.

REFERENCES:
patent: 3387276 (1968-06-01), Reichow
patent: 3737870 (1973-06-01), Carter et al.
patent: 3999051 (1976-12-01), Petschauer
Sager and Sutton, System Correction of Alpha-Particle-Induced Uncorrectable Error Conditions, IBM Technical Discl. Bulletin, vol. 23, No. 9, Feb. 1981, pp. 4225-4227.

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