Patent
1995-11-29
1998-05-12
Decady, Albert
395488, G06F 1100
Patent
active
057519390
ABSTRACT:
A mechanism for returning a computer system to a consistent, periodically updated state in main memory without constraining normal computer operation is provided, thereby enabling a computer system to recover from faults without loss of data or processing continuity. In a typical computer system, a processor and input/output elements are connected to a main memory subsystem that includes a primary memory. A checkpoint memory element which may include one or more buffer memories, including a read buffer and a write buffer, and an exclusive-or memory block, is also appended to this main memory subsystem. The exclusive-or memory block is a block of memory corresponding in size to one block of the primary memory that can fail as a unit. The exclusive-or memory block contains an exclusive-or of the contents of the primary memory at a previous checkpoint state. During normal processing, both or either a pre-image and/or a post image of data written to primary memory may be captured by the checkpoint memory element. In one embodiment, a write operation is converted to a read-then-write operation to store pre-image data in a FIFO. An exclusive-or of pre-image and post-image data is exclusive-or'ed into the exclusive-or memory. When a fault occurs in the computer system, the data stored in the buffer memories, along with the contents of the exclusive-or memory block, are used to ensure that the primary memory is restored to a previous checkpointed state from which the computer system can recover. This structure and protocol can guarantee a consistent state in the primary memory, thus enabling fault-tolerant operation.
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De'cady Albert
Texas Micro, Inc.
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