Main memory system and checkpointing protocol for a fault-tolera

Details Main memory system and checkpointing protocol for a fault-tolera Main memory system and checkpointing protocol for a fault-tolera

1995-11-29

1998-04-28

Decady, Albert

771162, G06F 1100

Patent

active

057456720

ABSTRACT:
A mechanism for maintaining a consistent, periodically updated state in main memory without constraining normal computer operation is provided, thereby enabling a computer system to recover from faults without loss of data or processing continuity. In a typical computer system, a processor and input/output elements are connected to a main memory subsystem that includes a primary memory. In embodiments of the present invention, a read buffer is also appended to this main memory subsystem. During normal processing, a pre-image of data written to the primary memory may be captured by the read buffer. Data captured in the read buffer can restore the system to a previous checkpoint. This structure and protocol can guarantee a consistent state in main memory, thus enabling fault-tolerant operation.

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