Main memory access in a microprocessor system with a cache memor

Details Main memory access in a microprocessor system with a cache memor Main memory access in a microprocessor system with a cache memor

1987-10-30

1989-07-11

Zache, Raulfe B.

Boots, shoes, and leggings

36518905, 365203, 3652385, 3642434, G06F 1208

Patent

active

048477583

ABSTRACT:
A data processing system includes a high speed buffer, or cache, memory for temporarily storing recently executed instructions and a slower main memory in which is stored the system's operating program. Rather than sequentially accessing the cache memory to determine if the next instruction is stored therein and then accessing the main memory if the cache memory does not have the next instruction, system operating speed is increased by simultaneously accessing the cache and main memories. By accessing the main memory during its row address strobe (RAS) precharge time while simultaneously accessing the cache memory, the time necessary for the system's processor unit (PU) to read the next instruction from the main memory when not stored in the cache memory is substantially reduced.

REFERENCES:
patent: 4138740 (1979-02-01), Itoh
patent: 4567578 (1986-01-01), Cohen et al.

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