Main bus interface package

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G06F 304

Patent

active

044197241

ABSTRACT:
In a data processing system having a plurality of units and a priority controller for controlling access to a bus by any of the units, each of the units is provided with a lock register having a stage corresponding to each unit connected to the bus. Each word placed on the bus by a source unit includes a lock bit which, in each unit except the source and destination units, sets the stages of the lock registers corresponding to the source and destination units. When a stage of a lock register is set it prevents the unit in which the register is located from attempting to communicate with a unit whose stage of the lock registers is set. On the last transmission between two units the word placed on the bus has a false lock bit which resets the stages of all of the lock registers corresponding to the source and destination units.

REFERENCES:
patent: 3348210 (1967-10-01), Ochsner
patent: 3462744 (1969-08-01), Tomasulo et al.
patent: 3735365 (1973-05-01), Nakamura et al.
patent: 3919693 (1975-11-01), Anderson
patent: 3984819 (1976-10-01), Anderson
patent: 3993981 (1976-11-01), Cassarino, Jr. et al.
patent: 3995258 (1976-11-01), Barlow
patent: 3997896 (1976-12-01), Cassarino, Jr.
patent: 4001790 (1977-11-01), Barlow
patent: 4038644 (1977-07-01), Duke et al.
patent: 4065809 (1977-12-01), Matsumoto
Ansi Tec. Committee X3T9 Minicomputer Project 54, "USA Contribution to ISO TC97/SC13 for a Small Computer-to-Peripheral Bus Interface Standard, Dec. 12, 1978.

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