Mailing system interface between a scale system processor and a

Details Mailing system interface between a scale system processor and a Mailing system interface between a scale system processor and a

1982-09-30

1986-04-15

Shaw, Gareth D.

Boots, shoes, and leggings

G06F 300

Patent

active

045831955

ABSTRACT:
In a mailing system including a postage value determining system processor which communicates along parallel channels and peripheral subsystem processors adapted to communicate with a system processor along a serial data bus, an interface is provided between the system processor and the serial bus. The interface includes a first and a second communications processor. The first processor is programmed to communicate with the system processor and with the second communications processor. The second communications processor is programmed to communicate with the first processor and with peripheral subsystem processors through the serial bus. Data and control signals are transmitted between the communications processors through an interprocessor channel. The interprocessor channel includes lines connected to reference voltage levels for providing appropriate signal levels for recognition by the communications processors which operate on different voltage signal levels.

REFERENCES:
patent: 4188664 (1980-02-01), Deshon
patent: 4271470 (1981-06-01), Dlugos et al.
patent: 4272819 (1981-06-01), Kalsumato
patent: 4395756 (1983-07-01), Daniels
patent: 4417320 (1983-11-01), Ei
patent: 4466079 (1984-08-01), Daniels et al.
patent: 4509164 (1985-04-01), Mouftah

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