Magnetoresistive random access memory with improved layout...

Details Magnetoresistive random access memory with improved layout... Magnetoresistive random access memory with improved layout...

2006-09-19

2010-10-05

Hoang, Quoc D (Department: 2894)

Semiconductor device manufacturing: process

Making device or circuit responsive to nonelectrical signal

C257S421000

Reexamination Certificate

active

07807492

ABSTRACT:
A MRAM memory and process thereof is described. A GMR magnetic layer is patterned to form a memory bit layer and an intermediate conductive layer. The intermediate conductive layer is disposed between two conductive layers such that shallow metal plugs can be utilized to interconnect the intermediate conductive layer and the conductive layers. Thus, a conventional deep tungsten plug process, interconnecting two conductive layers, is eliminated.

REFERENCES:
patent: 2005/0270831 (2005-12-01), Witcraft et al.
patent: 2006/0102970 (2006-05-01), Butcher et al.

Affiliated with

Also associated with

Rating

Magnetoresistive random access memory with improved layout... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Magnetoresistive random access memory with improved layout..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Magnetoresistive random access memory with improved layout... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4242122