Magnetoresistance random access memory for improved scalability

Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Heterojunction formed between semiconductor materials which...

Reexamination Certificate

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C365S171000, C365S173000, C365S158000, C257S295000

Reexamination Certificate

active

06531723

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to semiconductor memory devices.
More particularly, the present invention relates to semiconductor random access memory devices that utilize a magnetic field.
BACKGROUND OF THE INVENTION
Memory devices are an extremely important component in electronic systems. The three most important commercial high-density memory technologies are SRAM, DRAM, and FLASH. Each of these memory devices uses an electronic charge to store information and each has its own advantages. SRAM has fast read and write speeds, but it is volatile and requires large cell area. DRAM has high density, but it is also volatile and requires a refresh of the storage capacitor every few milliseconds. This requirement increases the complexity of the control electronics.
FLASH is the major nonvolatile memory device in use today. Typical non-volatile memory devices use charges trapped in a floating oxide layer to store information. Drawbacks to FLASH include high voltage requirements and slow program and erase times. Also, FLASH memory has a poor write endurance of 10
4
-10
6
cycles before memory failure. In addition, to maintain reasonable data retention, the thickness of the gate oxide has to stay above the threshold that allows electron tunneling, thus restricting FLASH's scaling trends.
To overcome these shortcomings, new magnetic memory devices are being evaluated. One such device is magnetoresistive RAM (hereinafter referred to as “MRAM”). MRAM has the potential to have speed performance similar to DRAM. To be commercially viable, however, MRAM must have comparable memory density to current memory technologies, be scalable for future generations, operate at low voltages, have low power consumption, and have competitive read/write speeds.
For an MRAM device, the stability of the memory state, the repeatability of the read/write cycles, and the memory element-to-element switching field uniformity are three of the most important aspects of its design characteristics. A memory state in MRAM is not maintained by power, but rather by the direction of the magnetic moment vector. Storing data is accomplished by applying magnetic fields and causing a magnetic material in a cell to be magnetized into either of two possible memory states. Recalling data is accomplished by sensing the electrical resistance, which differs for the two states. The magnetic fields for programming are created by passing currents through conductive lines external to the magnetic structure or through the magnetic structures themselves.
Conventional MRAM devices rely on the bit shape with aspect ratio to create a shape anisotropy that provides the switching field. As the bit dimension shrinks, three problems occur. First, the switching field increases for a given shape and film thickness, requiring more current to switch. Second, the total switching volume is reduced so that the energy barrier for reversal, which is proportional to volume and switching field, is also reduced. The energy barrier refers to the amount of energy needed to switch the magnetic moment vector from one state to the other. The energy barrier determines the data retention and error rate of the MRAM device and unintended reversals can occur due to thermal fluctuations if the barrier is too small. Finally, because the switching field is produced by shape, the switching field becomes more sensitive to shape variations as the bit shrinks in size. With photolithography scaling becoming more difficult at smaller dimensions, MRAM devices will have difficulty maintaining tight switching distributions.
It would be highly advantageous, therefore, to remedy the foregoing and other deficiencies inherent in the prior art.
Accordingly, it is an object of the present invention to provide a new and improved magnetoresistive random access memory device.
It is an object of the present invention to provide a new and improved magnetoresistive random access memory device which can be scaled while keeping the switching field nearly constant.
It is another object of the present invention to provide a new and improved magnetoresistive random access memory device which has a controllable magnetic switching volume.
It is a further object of the present invention to provide a new and improved magnetoresistive random access memory device which has a controllable energy barrier to minimize the bit error rate of the device.
It is an object of the present invention to provide a new and improved magnetoresistive random access memory device which can be fabricated using conventional photolithography processing.
It is another object of the present invention to provide a new and improved magnetoresistive random access memory device which has a switching field that is less dependant on shape.
SUMMARY OF THE INVENTION
To achieve the objects and advantages specified above and others, a scalable magnetoresistive tunneling junction memory (hereinafter referred to as “MRAM”) device is disclosed. The MRAM device includes a substrate onto which a fixed magnetic region is positioned. An electrically insulating material of sufficient thickness to act as a electron tunneling barrier is then positioned on the fixed magnetic region and a free magnetic region is positioned on the electrically insulating material. The fixed magnetic region adjacent to the tunneling barrier has a resultant magnetic moment vector that is fixed in a preferred direction.
In the preferred embodiment, the free magnetic region includes a synthetic anti-ferromagnetic (hereinafter referred to as “SAF”) layer material. The synthetic anti-ferromagnetic layer material includes N anti-ferromagnetically coupled layers of a ferromagnetic material where N is an integer greater than or equal to two. Further, the N layers define a magnetic switching volume that can be adjusted by changing N. In the preferred embodiment, the N ferromagnetic layers are anti-ferromagnetically coupled by sandwiching an anti-ferromagnetic coupling spacer layer between each adjacent ferromagnetic layer.
In the preferred embodiment, the total net magnetic moment vector is comprised of the vector sum of the each N sub-layer magnetic moment vectors. Because each sub-layer is anti-ferromagnetically coupled to its neighboring layer, there are two antiparallel directions the sub-layer moments can point in zero magnetic field. The total moment is therefore determined by the difference of M
1
and M
2
, where M
1
and M
2
are the total sub-layer moments in each direction, respectively. The magnetic moment vectors are usually oriented anti-parallel by the coupling of the anti-ferromagnetic coupling spacer layer. Anti-ferromagnetic coupling is also generated by the magnetostatic fields of the layers in the MRAM structure. Therefore, the spacer layer need not necessarily provide any additional antiferromagnetic coupling beyond eliminating the ferromagnetic coupling between the two magnetic layers.
The magnetic moment vectors in the ferromagnetic layers can have different magnitudes to provide a resultant magnetic moment vector given by &Dgr;M=(M
2
−M
1
) and a sub-layer magnetic moment fractional balance ratio,
M
br
=
(
M
2
-
M
1
)
(
M
2
+
M
1
)
=
Δ



M
M
total
,
where M
total
=M
1
+M
2
is the total moment of the N layers. The resultant magnetic moment vector of the N-layer structure is free to rotate with an applied magnetic field. In zero field the resultant magnetic moment vector will be stable in a direction, determined by the magnetic anisotropy, which is either parallel or anti-parallel with respect to the resultant magnetic moment vector of the fixed magnetic region.
The current through the MRAM device depends on the tunneling magnetoresistance, which is governed by the relative orientation of the magnetic moment vectors of the free and fixed magnetic regions directly adjacent to the tunneling barrier. If the magnetic moment vectors are parallel, then the MRAM device resistance is low and a voltage bias will induce a larger current through the device. This state is defined as a “1”. I

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