Magnetically controlled logic cell

Details Magnetically controlled logic cell Magnetically controlled logic cell

1996-09-18

1998-04-21

Levy, Stuart S.

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

With particular power supply distribution means

257421, 257427, H01L 2982, H01L 4300, H01L 2710

Patent

active

057420807

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

The present invention relates to the field of microelectronics and more particularly to magnetically controlled integrated circuits and could be used for building up memory cells and in sensor control devices.
There are known magnetically controlled logic cells with operating principle based on changing of output signal in effect with external magnetic field. They constitute devices comprising a transformer of magnetic field into electric signal and an electronic circuit of processing the signal placed in a single semiconductor crystal. The most common transformer of magnetic field into electric signal is a Hall element, operating principle of which is based on developing the EMF between two contacts located on the opposite sides of a rectangular semiconductor sample placed in the magnetic field, with electric current running between two contacts located on another sides of the semiconductor.
The EMF forming by the Hall element in a magnetically controlled logic cell is passed to the input of an integrated circuit and results in forming the signal on circuit output which is, depending on the intensity of the magnetic field, corresponding to a logical 0 or logical 1. The magnetically controlled cell with Hall element is usually produces of silicon using the conventional epitaxial-planar technology (U.S. Pat. No. 3,816,766, M.cl.GIIC 11/40, publ. in 1974).
The common drawbacks of the existing magnetically controlled logic cells is their insufficient magnetic sensitivity and high level of power consumption. The first leads to impossibility of using this logic cell in low intensity magnet fields (on the order of one milli-Tesla) without complicating of the electronic circuit, mostly by adding amplifying stages. The second drawback is associated with high value of electric current running through the Hall element in a state of waiting for magnetic signal. This drawback also considerably restricts the practical application of the magnetically controlled logic cells.
The mentioned drawbacks are directly associated with the value of electric resistance of the Hall element. In the present invention it is proposed a design of the magnetically controlled logic cell which provides the increasing of the electric resistance of the Hall element resulting in increasing of magnetic sensitivity and decreasing of power consumption.


SUMMARY OF THE INVENTION

It is an object of the present invention to increase the magnetic sensitivity and to decrease the power consumption of the magnetically controlled logic cells.
This object is achieved by that way that the magnetically controlled logic cell comprises a semiconductor substrate of the first type conductivity, eight alloyed regions of the second type conductivity creating in pairs drain and source regions of four field-effect transistors, a dielectric film arranged on the surface of the substrate having openings over each of the drain and source regions, eight conducting contact regions located over the drain and source regions on their surface and on the surface of the dielectric film, four conducting gate regions each situated on the surface of the dielectric film between the drain and source regions of each transistor, four current supply buses arranged on the surface of the dielectric film, the first of which is adjoining the source regions of the first and second transistors and being a power supply bus, the second one is adjoining the source and gate regions of the third and fourth transistors and being a power supply bus, the third one is adjoining the gate region of the first transistor, source regions of the second and fourth transistors and being an output bus, the fourth one is adjoining the gate region of the second transistor, source regions of the first and third transistors and being an output bus, the substrate of the first type conductivity comprises a concealed dielectric region, insulating region arranged on the perimeter of the concealed dielectric region and adjoining it and the dielectric film, four highly alloyed regions o

REFERENCES:
patent: 3816766 (1974-06-01), Anselino et al.
patent: 4677380 (1987-06-01), Popovic et al.
patent: 5245227 (1993-09-01), Furtek et al.
patent: 5329480 (1994-07-01), Wu et al.
patent: 5572058 (1996-11-01), Biard
patent: 5614754 (1997-03-01), Inoue
patent: 5627398 (1997-05-01), Zlebir et al.

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