Semiconductor device manufacturing: process – Having magnetic or ferroelectric component
Reexamination Certificate
2002-08-30
2004-10-26
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Having magnetic or ferroelectric component
C438S005000, C257S421000
Reexamination Certificate
active
06808940
ABSTRACT:
BACKGROUND
Generally, a memory chip comprises a plurality of memory cells which are etched onto a silicon wafer and addressable via an array of column conducting leads (bit lines) and row conducting leads (word lines). That is, the intersection of a bit line and a word line typically constitutes the address of a memory cell. The memory cells are controlled by specialized circuits that perform functions such as identifying rows and columns of memory cells to read data from or write data to. Typically, each memory cell stores data in the form of a “1” or a “0,” representing a bit of data.
An array of magnetic memory cells is often called magnetic random access memory or MRAM. MRAM is generally nonvolatile memory (i.e., a solid state chip that retains data when power is turned off). At least one type of magnetic memory cell includes a data layer and a reference layer that is separated from the data layer by an intermediate layer. The data layer may also be referred to as a bit layer, a storage layer, a sense layer, and/or other known terminology. In a magnetic memory cell, a bit of data (e.g., a “1” or “0”) may be stored by “writing” into the data layer via one or more conducting leads (e.g., a bit line and a word line). The write operation is typically accomplished via a write current that sets the orientation of the magnetic moment in the data layer to a predetermined direction.
Once written, the stored bit of data may be read by providing a read current through one or more conducting leads (e.g., a read line) to the reference layer. In at least one type of magnetic memory cell, the read current sets the orientation of the magnetic moment of the reference layer in a predetermined direction. For each memory cell, the orientations of the magnetic moments of the data layer and the reference layer are either parallel (in the same direction) or anti-parallel (in different directions) to each other. The degree of parallelism affects the resistance of the cell, and this resistance can be determined by sensing (e.g., via a sense amplifier) an output current produced by the memory cell in response to the read current.
More specifically, if the magnetic moments are parallel, the resistance determined based on the output current is of a first relative value (e.g., relatively low). If the magnetic moments are anti-parallel, the resistance determined is of a second relative value (e.g., relatively high). The relative values of the two states (i.e., parallel and anti-parallel) are typically different enough to be sensed distinctly. A “1” or a “0” may be assigned to the respective relative resistance values depending on design specification.
In at least one type of magnetic memory cells, the data layer and the reference layer are implemented using differing magnetic hardnesses. For example, the data layer may be magnetically harder and the reference layer may be magnetically softer. A harder layer typically has a relatively fixed magnetic state and its magnetic moment is oriented in one direction. It takes a relatively greater current to reverse the direction of the magnetic moment in a hard layer. The magnetic moment orientation in the soft layer is more readily reversible. The intermediate layer may comprise a non-magnetic conductive material and is usually thick enough to prevent exchange coupling between the data and reference layers. The various conducting leads which are used to address the memory cells (e.g., bit lines, word lines, and read lines), and to provide currents to pass through the data and reference layers to read data from or write data to the memory cells are provided by one or more additional layers, called conducting layer(s).
The layers described above and their respective characteristics are typical of magnetic memory cells based on tunneling magnetoresistance (TMR) effects known in the art. Other combinations of layers and characteristics may be used to make magnetic memory cells based on TMR effects. For example, a pinned reference layer and an anti-ferromagnetic layer may be used in place of the soft reference layer described above. This configuration of TMR memory cells is well known in the art and need not be described in more detail herein. See, for example, U.S. Pat. No. 6,404,674, issued to Anthony et al., and co-pending U.S. application Ser. Nos.: (1) 09/825093, entitled “Cladded Read Conductor For A Pinned-On-The-Fly Soft Reference Layer”, filed on Apr. 2, 2001; and (2) 09/963171, entitled “Magneto-Resistive Device Having Soft Reference Layer”, filed on Sep. 25, 2001, which are hereby incorporated by reference in their entirety for all purposes.
Still other configurations of magnetic memory cells based on other well known physical effects (e.g., giant magnetoresistance (GMR), anisotropic magnetoresistance (AMR), colossal magnetoresistance (CMR), and/or other physical effects) may be implemented with various embodiments described herein.
Throughout this application, various exemplary embodiments will be described in reference to the TMR memory cells having a relatively hard data layer, and relative soft reference layer, as described above. Those skilled in the art will readily appreciate that the exemplary embodiments may also be implemented with other types of magnetic memory cells known in the art (e.g., other types of TMR memory cells, GMR memory cells, AMR memory cells, CMR memory cells, etc.) according to the requirements of a particular implementation.
Generally speaking, desirable characteristics for any configuration of memory device include increased speed, reduced power consumption, and/or lower cost. Lower cost may be achieved by a simpler fabrication process and/or a smaller chip surface area. As the size of memory cells is reduced, however, fringe (and/or stray) magnetic fields emanating from a target memory cell during a read or write operation may cause increased magnetic interference among neighboring memory cells. Depending on the proximity of magnetic memory cells to each other and the magnitude of currents being used for read and write operations, fringe magnetic fields may even corrupt a data bit stored in the data layer of a neighboring magnetic memory cell that was not targeted for the read or write operations.
Thus, a market exists for a MRAM device in which fringe magnetic fields generated by a magnetic memory cell are materially controlled so as to reduce interference with nearby memory cells. This is especially useful in (although not limited to) high density MRAM devices.
SUMMARY
In a magnetic memory array comprising a plurality of magnetic memory cells, each of the magnetic memory cells includes a data layer and a reference layer, such that a value stored in the data layer is determinable by measuring a relative orientation of the magnetic moments of the data layer and the reference layer and each magnetic memory cell during operation emanates fringe magnetic fields potentially influencing nearly magnetic memory cells. An improvement comprises a magnetic shielding disposed adjacent to at least one of the magnetic memory cells to reduce magnetic interference with respect to another of the magnetic memory cells, and an insulator disposed as to separate at least a portion of the magnetic shielding from the at least one magnetic memory cell.
In various exemplary embodiments to be described herein, the magnetic shielding includes a magnetic shield layer, patterned magnetic shield materials, and/or magnetic particles embedded within the insulating oxide.
A method for reducing magnetic interference between at least two memory cells in a magnetic memory array device comprises creating a desired magnetic field within at least one magnetizable layer of a first memory cell by providing a current through the layer and reducing an undesirable magnetic interference between the first memory cell and a second memory cell by absorbing a fringe magnetic field emanating from the first memory cell via a magnetic shield material located in proximity to the first memory cell.
REFERENCES:
patent: 6509621 (2003-01-01), Nakao
Bhattacharyya Manoj
Sharma Manish
Berry Renee R
Hewlett--Packard Development Company, L.P.
Nelms David
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