Magnetic semiconductor memory device

Static information storage and retrieval – Read only systems – Magnetic

Reexamination Certificate

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C257S295000

Reexamination Certificate

active

07002831

ABSTRACT:
A memory cell in a so-called MRAM by utilizing a tunnel magnetic resistance in the prior art has raised problems that a magnetic field to be applied to a TMR element is essentially weak since a word line for write is disposed apart from the TMR element, that a large current is required at the time of a writing operation, and that electric power consumption is large. In order to solve the above-described problems experienced in the prior art, the present invention provides an MRAM memory cell structure and its fabricating method in which a word line for write is disposed near a TMR element and surrounds it in three directions.

REFERENCES:
patent: 6560135 (2003-05-01), Matsuoka et al.
patent: 6771535 (2004-08-01), Sakata et al.
patent: 6876523 (2005-04-01), Takahashi et al.
patent: 2002/0093845 (2002-07-01), Matsuoka et al.
patent: 2002-208682 (2002-07-01), None
Durlam et al., “A low power 1Mbit MRAM based on 1T1MTJ bit cell integrated with Copper Interconnects,” 2002 Symposium on VLSI Circuits Digest of Technical Papers, pp. 160-163.

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