Static information storage and retrieval – Read only systems – Magnetic
Reexamination Certificate
2001-08-23
2003-05-06
Nelms, David (Department: 2818)
Static information storage and retrieval
Read only systems
Magnetic
C365S171000, C365S173000
Reexamination Certificate
active
06560135
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory apparatus. More particularly, the present invention relates to a non-volatile random access memory (RAM) having a high speed by utilizing a magneto-resistance effect.
2. Description of the Prior Art
In a dynamic random access memory (DRAM) which has realized an improvement of integration at a rate of four times per three year, a demand thereof is going to be improved more and more hitched to an explosive sale of personal computers in recent years. A mass production of 64 megabit DRAM has passed the peak, and a development intending to achieve a mass production of 256 megabit DRAM using 0.16 &mgr;m or less size corresponding to a next-generation micro-fabrication technique has been making progress.
A memory cell from the 16 Kb DRAM to the DRAM produced presently is, as shown in
FIG. 1
, constituted by a transistor corresponding to a switch and a capacitor accumulating an information electric charge, and is called as
1
transistor cell. In this memory cell, a signal electric voltage read out to a data line is determined on the basis of a ratio between a capacitor capacitance Cs and a parasitic capacitance Cd. Further, since the information electric voltage of the cell is charged to the electric voltage of the data line by reading out the information, it corresponds to a destructive readout, so that a refresh operation corresponding to a rewriting of the data is required.
A greatest problem in the memory cell is to secure a necessary and sufficient capacitor capacitance Cs in two points of view comprising a cell signal electric voltage and a soft error endurance. In order to solve the problem, the memory cell becomes a three-dimensional structure as shown in
FIG. 2
, and in order to secure a necessary and sufficient accumulating capacity, a height of the capacitor is continuously increased together with a refining. However, the increase of height of the capacitor generates a high step between a memory cell array portion and a peripheral circuit, and significantly reduces a process margin in addition to a lithography, thereby directly causing an increase of manufacturing cost. In the DRAM after 256 Mbit, it is essential that this problem becomes serious more and more. against this background, it is highly expected to provide a memory cell requiring no capacitor in place of the conventional
1
transistor cell.
A magnetic random access memory (MRAM) corresponds to a high speed non-volatile memory utilizing a tunnel magneto resistance (TMR) of a magnetic tunnel junction (MTJ) described later. IBM and Motorola respectively manufactured arrays of 1 Kb and 512 b MRAMs by way of trial and reported a confirmation of memory operations, in International Solid State Circuit Conference 2000 (ISSCC 2000). A description will be briefly given below of a principle of operation of the MRAM. At first, a description will be given of TMR of MTJ corresponding to a base of a memory function. MTJ is structured, for example, such that a thin tunnel insulating film
2
is held between two ferromagnetic layers
1
and
3
as shown in
FIG. 3. A
tunnel conductance of this structure is in proportion to a product of density of states in a fermi level of two ferromagnetic materials.
FIG. 4
shows in a comparative manner a density of states in the case (a) of parallel spin direction of two ferromagnetic materials are parallel to each other and the case (b) of anti-parallel spin direction. Since the directions of the spins are stored before and after tunneling, a tunnel resistance is small in the case of being parallel and on the contrary, it is large in the case of being anti-parallel, as is apparent from FIG.
4
. As a result, when fixing the direction of one spin in the magnetic tunnel junction and changing the direction of another spin due to an external magnetic field, it is known that a hysteresis characteristic shown in
FIG. 5
appears and a memory is obtained. Since a switching of the spin has an order of nsec, and the direction of the spin is fixed unless the magnetic field is applied, an operation of the high speed non-volatile memory is expected.
FIGS. 6 and 7
respectively show an equivalent circuit of the MRAM announced by IBM and the like and a simplified cross sectional structure. A memory cell is constituted by a selective transistor and a TMR device. Except for the TMR device employed in place of the capacitor, it is similar to the existing DRAM. A primary difference from the DRAM is that surplus word lines
7
and
701
are provided.
In order to clarify the reason, a description will be given of a writing and readout operation in the MRAM shown in
FIGS. 6 and 7
. At a time of writing, an electric current is applied to bit lines
6
and
601
and the writing word lines
7
and
701
, the direction of the spin is written in the selected cell due to a generated total magnetic field. In the non-selected cells, since an applied magnetic field is small, the directions of the spins are not changed. At a time of reading out, readout word lines
8
and
801
are turned on, and it is judged on the basis of the electric current flowing between common ground lines
13
and
1301
and the bit lines
6
and
601
whether “0” or “1” is established.
In the MRAM announced by IBM and the like mentioned above, the writing word lines
7
and
701
are formed below the bit lines
6
and
601
, and this structure has the following two problems. One of them is that a process becomes hard, and another of them is that a data writing becomes unstable. This will be described below.
FIG. 8
shows a cross sectional view at a time of actually putting the MRAM having the structure shown in
FIG. 7
into practice. In this case, there is shown the case that the word line pitch is made minimum, that is, the cell area is made minimum. In the present structure, it is necessary to open a contact with passing through a portion between the writing word lines without electrically shorting with the writing word lines
702
so as to connect plugs
1105
and
1104
, and this is hard in view of process. Further, as shown in
FIG. 9
, since an overlap between the writing word line
702
and the TMR device
502
on a plane at a time of viewing from the above is partly formed, the write magnetic field is not uniformly applied to a whole of the TMR device
502
, and it becomes unstable to write the data. These two problems are both generated by a reason that the writing word line
702
is formed below the bit line
602
.
SUMMARY OF THE INVENTION
In order to solve the problem mentioned above, in accordance with an embodiment of the present invention, there is provided an MRAM structure in which a writing word line is formed above a bit line. The present structure solves two problems mentioned above increasing a cell area.
In accordance with the present invention, in addition to having the structure of the MRAM in which the writing word line is formed above the bit line, it is possible to form a plug connected to a TMR device without applying a self-aligned contact opening process. This is easy in view of process in comparison with the case mentioned above. Further, since a restriction of layout of the writing word line is reduced, the writing word line can cover the TMR device at a time of viewing from the above. This is advantageous in a point of view of a stability for writing the data.
REFERENCES:
patent: 6351408 (2002-02-01), Schwarzl et al.
patent: 6359805 (2002-03-01), Hidaka
patent: 6392924 (2002-05-01), Liu et al.
Itoh Kiyoo
Matsuoka Hideyuki
Sakata Takeshi
Watanabe Katsuro
Antonelli Terry Stout & Kraus LLP
Auduong Gene N.
Hitachi , Ltd.
Nelms David
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