Magnetic random access memory using memory cells with...

Details Magnetic random access memory using memory cells with... Magnetic random access memory using memory cells with...

2003-05-28

2004-11-09

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S225500, C365S173000, C365S171000, C365S158000, C365S051000, C365S066000

Reexamination Certificate

active

06816431

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to memory circuits, and more particularly relates to a magnetic random access memory (MRAM) circuit employing rotated magnetic storage elements.
BACKGROUND OF THE INVENTION
FIG. 1A
illustrates a conventional magnetic tunnel junction (MTJ) device
100
. The MTJ
100
is typically comprised of a stack of two ferromagnetic layers (ML) separated by a tunnel barrier (TL) at a cross-point of two conductors, one of which may be a word line (WL) and the other a bit line (BL). One of the two magnetic layers is often referred to as a free magnetic layer. The magnetic orientation of the free magnetic layer can be changed by the superposition of magnetic fields generated by programming currents I
WL
and I
BL
flowing in the conductors WL and BL, respectively. The other of the two magnetic layers ML is often referred to as a fixed magnetic layer. The programming currents I
WL
and I
BL
cannot change the magnetic orientation of the fixed magnetic layer. The logical state (e.g., a “0” bit or a “1” bit) is stored in the MTJ
100
by changing the orientation of the free magnetic layer relative to the fixed magnetic layer. When both magnetic layers have the same orientation
102
, the MTJ
100
typically has a low resistance R
C
associated therewith, as measured between conductors WL and BL, and in this case R
C
is more specifically referred to as R
parallel
. Likewise, the resistance R
C
of the MTJ
100
is generally high when the magnetic layers are oriented in opposite directions
104
with respect to one another, and in this case R
C
is more specifically referred to as R
antiparallel
.
A single bit of information may be selectively written into an MTJ memory cell embedded within a two-dimensional array of such cells by applying coincident and orthogonal magnetic fields within the plane of the MTJ. In conventional MTJ MRAM, the programming currents I
WL
and I
BL
generate a hard axis field and an easy axis field, respectively, that change the magnetic orientation of the free magnetic layer, ML (free). The current I
BL
generates the easy axis field that partially selects the MTJ memory cell to be written. Of equal significance, the sign Of I
BL
sets the state of the selected MTJ memory cell. Hence, the write current flowing through the bit line BL, namely, I
BL
, must flow conditionally in one of two directions, and will be referred to henceforth as a bidirectional write current. The current I
WL
generates the hard axis field that partially selects the MTJ memory cell to be written. In contrast to I
BL
, the write current flowing through the word line WL, namely, I
WL
, need only flow in one direction and will be referred to henceforth as a write select current.
A conventional MRAM generally includes a plurality of MTJ devices connected in an array configuration.
FIG. 1B
illustrates a conventional cross-point memory array, wherein each memory cell comprises a single MTJ device coupled at an intersection of a word line (e.g., WL
k−1
, WL
k
, WL
k+1
) and a corresponding bit line (e.g., BL
i−1
, BL
i
, BL
i+
). MRAM circuits are discussed in further detail, for example, in the article by W. Reohr et al., entitled “Memories of Tomorrow,”
IEEE Circuits and Devices Mag.,
pp. 17-27, Vol. 18, No. 5, September 2002, which is incorporated herein by reference.
Generally, within the cross-point memory array, the write select current is required to aid in the selection of one or more memory cells in the array. One or more bidirectional write currents, corresponding to one or more respective memory cells of a one or more bit word, are required for writing the selected memory cells to a zero or one logical state. Word lines and bit lines routed throughout the memory array convey the programming current and sense current for writing and reading, respectively, selected memory cells in the array.
In a conventional cross-point MRAM device, during a read operation, the bit lines convey the sense current between a sense amplifier and the memory cell to read the state of the memory cell. During a write operation, the bit lines convey the bidirectional write current in close proximity to the MTJ device of the selected memory cell to write the selected memory cell, while a word line simultaneously conveys the write select current in close proximity to the aforementioned MTJ device to write the selected memory cell.
Since the sense current is substantially smaller in magnitude than either of the programming currents (e.g., about 50 microamperes versus about 5 milliamperes, respectively), the sense current is considerably more sensitive to noise. Additionally, the read access time of the memory array depends, to a large extent, on reliably extracting the state of the memory cell from this relatively small sense current. Consequently, the number of memory cells that can be placed along a given bit line should be limited to minimize the read access time of the memory array.
Since the supply voltage applied to modem memory devices is typically constrained to below three volts and the sheet resistance of metal interconnects is typically close to about 0.1 ohm, the large programming currents required in the memory array limit the number of memory cells that can be placed along the bit line or word line dimensions. Therefore, reducing the number of memory cells along a bit line dimension to increase read access time, as previously stated, without also increasing the number of memory cells along a word line dimension would undesirably reduce the array efficiency, which can be defined as a percentage of the total semiconductor area devoted to the memory cells.
There exists a need, therefore, for an improved MRAM circuit which provides an increased read access time without significantly reducing the array efficiency of the MRAM device. Furthermore, it would be desirable to provide an improved 1T1MTJ (one transistor/one MTJ) HAM circuit that enables a smaller memory cell size to be realized.
SUMMARY OF THE INVENTION
The present invention provides techniques for forming an MRAM circuit having a plurality of memory cells advantageously arranged such that a read line and a corresponding write line associated with a given memory cell are spatially separated from one another at least in part to enable optimization of read and write operations. The techniques of the present invention may be further used for reducing the size of memory cells within a 1T1MTJ MRAM circuit. To accomplish these goals, at least a portion of a plurality of magnetic storage elements are selectively rotated, in comparison to conventional MRAM circuits, so that an easy axis associated with each of the magnetic storage elements is substantially parallel to a direction of sense current flow and a hard axis associated with the magnetic storage elements is substantially parallel to a direction of bidirectional write current flow.
In accordance with one aspect of the invention, a magnetic random access memory circuit comprises a plurality of magnetic memory cells, each of the memory cells including a magnetic storage element having an easy axis and a hard axis associated therewith, and a plurality of column lines and row lines for selectively accessing one or more of the memory cells, each of the memory cells being proximate to an intersection of one of the column lines and one of the row lines. Each of the magnetic memory cells is arranged such that the easy axis is substantially parallel to a direction of flow of a sense current and the hard axis is substantially parallel to a direction of flow of a write current. In this manner, the read and write ports associated with the memory circuit can be spatially separated from one another, thereby enabling the read and write operations to be independently optimized.
These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.


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