Static information storage and retrieval – Read only systems – Magnetic
Reexamination Certificate
2001-12-27
2003-04-01
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Read only systems
Magnetic
C365S171000, C365S173000
Reexamination Certificate
active
06542398
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a magnetic random access memory (abbreviated as ‘MRAM’), and in particular to an improved MRAM having a higher speed than an SRAM, integration density as high as a DRAM, and a property of a nonvolatile memory such as a flash memory.
DESCRIPTION OF THE BACKGROUND ART
Most of the semiconductor memory manufacturing companies have developed the MRAM using a ferromagnetic material as one of the next generation memory devices.
The MRAM is a memory device for reading and writing information. It has multi-layer ferromagnetic thin films, and operates by sensing current variations according to a magnetization direction of the respective thin film. The MRAM is high speed, has low power consumption and allows high integration density due to the special properties of the magnetic thin film. The MRAM also performs a nonvolatile memory operation similar to a flash memory.
The MRAM is a memory device which uses a giant magneto resistive (abbreviated as ‘GMR’) phenomenon or a spin-polarized magneto-transmission (SPMT) generated when the spin influences electron transmission. The MRAM using the GMR utilizes the phenomenon that resistance is remarkably varied when spin directions are different in two magnetic layers having a non-magnetic layer therebetween to implement a GMR magnetic memory device. The MRAM using the SPMT utilizes the phenomenon that larger current transmission is generated when spin directions are identical in two magnetic layers having an insulating layer therebetween to implement a magnetic permeable junction memory device.
However, the MRAM research is still in its early stage, and mostly concentrated on the formation of multi-layer magnetic thin films. Less of the research focuses on a unit cell structure and a peripheral sensing circuit.
FIG. 1
is a cross-sectional diagram illustrating a conventional MRAM.
Referring to
FIG. 1
, a gate electrode
33
, namely, a first word line is formed on a semiconductor substrate
31
. Source/drain junction regions
35
a
and
35
b
are formed on the semiconductor substrate
31
at both sides of the first word line
33
. A ground line
37
a
and a first conductive layer
37
b
are formed to contact the source/drain junction regions
35
a
and
35
b
. Here, the ground line
37
a
is formed in a patterning process of the first conductive layer
37
b.
Thereafter, a first interlayer insulating film
39
is formed to planarize the whole surface of the resultant structure, and a first contact plug
41
is formed to contact the first conductive layer
41
through the first interlayer insulating film
39
.
A second conductive layer which is a lower read layer
43
contacting the first contact plug
41
is then patterned.
A second interlayer insulating film
45
is formed to planarize the whole surface of the resultant structure, and a second word line, which is a write line
47
, is formed on the second interlayer insulating film
45
.
A third interlayer insulating film
48
is formed to planarize the upper portion of the second word line which is the write line
47
.
A second contact plug
49
is formed to contact the second conductive layer
43
.
A seed layer
51
is formed to contact the second contact plug
49
. Here, the seed layer
51
is formed to overlap between the upper portion of the second contact plug
49
and the upper portion of the write line
47
.
Thereafter, a semi-ferromagnetic layer (not shown), a pinned ferromagnetic layer
55
, a tunnel junction layer
57
and a free ferromagnetic layer
59
are stacked on the seed layer
51
, thereby forming a magnetic tunnel junction (MTJ) cell
100
which has a pattern size as large as the write line
47
and which overlaps the write line
47
as shown in FIG.
1
.
At this time, the semi-ferromagnetic layer prevents the magnetization direction of the pinned layer from being changed, and the magnetization direction of the tunnel junction layer
57
is fixed to one direction. The magnetization direction of the free ferromagnetic layer
59
can be changed by an external magnetic field, and information of ‘0’ or ‘1’ can be stored according to the magnetization direction of the free ferromagnetic layer
59
.
A fourth interlayer insulating film
60
is formed over the resultant structure, and planarized to expose the free ferromagnetic layer
59
. An upper read layer, namely a bit line
61
is formed to contact the free ferromagnetic layer
59
.
Still referring to
FIG. 1
, the operation of the MRAM will now be described. The unit cell of the MRAM includes one field effect transistor having the first word line (which is a read line) used to read information, the MTJ cell
100
, the second word line
47
(which is a write line) determining the magnetization direction of the MTJ cell
100
by forming an external magnetic field by applying current, and the bit line
61
which is an upper read layer determining the magnetization direction of the free layer by applying current to the MTJ cell
100
in a vertical direction.
Here, during the operation of reading the information from the MTJ cell, a voltage is applied to the first word line
33
as the read line, thereby turning the field effect transistor on. By sensing a magnitude of current applied to the bit line
61
, the magnetization direction of the free ferromagnetic layer
59
in the MTJ cell is detected.
During the operation of storing the information in the MTJ cell, while maintaining the field effect transistor in the off state, the magnetization direction in the free ferromagnetic layer
59
is controlled by a magnetic field generated from applying current to the second word line
47
(which is the write line) and the bit line
61
. At this time, when current is applied to the bit line
61
and the write line
47
at the same time, the generated magnetic field is strongest at a vertical intersecting point of the two metal lines, and, thus, one cell can be selected from a plurality of cells.
The operation of the MTJ cell in the MRAM will now be described. When the current flows in the MTJ cell in a vertical direction, a tunneling current flows through an interlayer insulating film. When the tunnel junction layer and the free ferromagnetic layer have the same magnetization direction, the tunneling current increases. When the tunnel junction layer and the free ferromagnetic layer have different magnetization directions, the tunneling current decreases due to a tunneling magneto resistance (TMR) effect. A decrease in the magnitude of the current due to the TMR effect is sensed, and thus the magnetization direction of the free ferromagnetic layer is sensed, thereby detecting the information stored in the cell.
As described above, the conventional MRAM has disadvantages in that the whole fabrication process is complicated. Due to a number of fabrication steps and a stacked structure, productivity is reduced due to an increased cell area, and high integration of a semiconductor device is hardly achieved.
SUMMARY OF THE INVENTION
In accordance with an aspect of the invention, there is provided an MRAM including: a semiconductor substrate having an active region, the active region having a first side and a second side, a word line formed in the active region of the semiconductor substrate, the word line serving as a read line and a write line; a ground line and a lower read layer respectively formed at the first side and the second side of the active region of the semiconductor substrate; a seed layer formed to be in electrical communication with the lower read layer, the seed layer overlapping an upper portion of the word line; an MTJ cell contacting the upper portion of the seed layer at the upper portion of the word line; and a bit line contacting the MTJ cell, the bit line being perpendicular to the word line.
REFERENCES:
patent: 6272036 (2001-08-01), You et al.
patent: 2002/0006058 (2002-01-01), Nakajima et al.
patent: 2002/0084500 (2002-07-01), Kang et al.
Kang Chang Yong
Kim Chang-Shuk
Hoang Huan
Hynix / Semiconductor Inc.
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