Magnetic memory with tunnel junction memory cells and phase...

Active solid-state devices (e.g. – transistors – solid-state diode – Responsive to non-electrical signal – Magnetic field

Reexamination Certificate

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C257S108000, C257S295000, C257S423000, C257S427000

Reexamination Certificate

active

06653704

ABSTRACT:

TECHNICAL FIELD
This invention relates generally to magnetic random access memory (MRAM) arrays that use magnetic tunnel junction (MTJ) devices as the individual memory cells, and more particularly to an MRAM array with switching elements for controlling sense current to the MTJ cells during the read process.
BACKGROUND OF THE INVENTION
Magnetic tunnel junction (MTJ) devices have been proposed as memory cells for use in a nonvolatile magnetic random access memory (MRAM) arrays. An MTJ device is comprised of two ferromagnetic layers separated by a thin insulating tunnel barrier layer and is based on the phenomenon of spin-polarized electron tunneling. The insulating tunnel barrier layer is thin enough that quantum mechanical tunneling occurs between the ferromagnetic layers. The tunneling phenomenon is electron-spin dependent, making the magnetic response of the MTJ device a function of the relative orientations and spin polarizations of the two ferromagnetic layers. Usually the tunneling probability of the charge carriers is highest when the magnetic moment of the ferromagnetic layer are parallel to one another. Thus, in an MRAM the electrical resistance of an MTJ memory cell is in its lowest state when the magnetic moments or magnetizations of both ferromagnetic layers are parallel, and is in its highest state when the magnetic moments are antiparallel. The basic structure of an MTJ memory cell is described in detail in IBM's U.S. Pat. No. 5,650,598, which also describes an MTJ memory cell wherein one of the ferromagnetic layers has its magnetization fixed or pinned by being exchange coupled with an antiferromagnetic layer and the other ferromagnetic layer is free to have its magnetization rotated in the presence of a magnetic field.
The electrical leads of the MRAM array are referred to as the bit line and the word line. For writing to a cell, current is passed down the bit and word lines. The sum of the magnetic fields that are generated by the current flowing down both lines is able to switch the magnetization of the free ferromagnetic layer in that cell. No current passes through the cell while it is being written. However, during the read process sense current passes from the word line through the cell into the bit line. Depending on the relative orientation of the free and fixed ferromagnetic layers, the cell being read is in either a high or a low resistance state. One problem with an MTJ MRAM is that the cells that are not being read need to be in a significantly higher resistance state than the cells that are being read. Thus, IBM's patents U.S. Pat. No. 5,640,343 and 6,097,635 describe MRAM arrays with MTJ memory cells in series with electronic switching elements, such as diodes, to isolate specific memory cells so that the sense current passes only through the cells being read.
What is needed is an MTJ MRAM array that does not require electronic switching elements for each MTJ memory cell.
SUMMARY OF THE INVENTION
The invention is an MRAM array with a plurality of non-electronic switching elements, each switching element being located between the bit and word lines and in electrical series connection with an associated MTJ memory cell, to enable reading of the memory cells. The switching element is a layer of vanadium dioxide, a material that exhibits a first order phase transition at a transition temperature of approximately 65° C. from a low-temperature monoclinic (semiconducting) to a high-temperature tetragonal (metallic) crystalline structure. This phase transition is accompanied by a change in electrical resistance from high resistance at room temperature to low resistance above the transition temperature. To read a cell, the vanadium dioxide switching element associated with that cell is heated to lower the resistance of the switching element and thereby allow sense current to pass through the cell, thereby enabling the memory state of the cell to be read. Heating of the vanadium dioxide switching element is by application of a voltage pulse directly to the switching element to apply current to resistively heat the switching element. Alternatively, a separate resistive heater is located in electrical contact with or in close proximity to the vanadium dioxide switching element and current is applied to the resistive heater to directly or indirectly heat the switching element. One or more materials, such as Cr, Al, Ga and Ge, can be added in relatively small amounts to the vanadium dioxide to increase the transition temperature without affecting its crystalline structure.


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M. F. Becker et al., “Femtosecond laser excitation of the semiconductor-metal phase transition in VO2”, Appl. Phys. Lett., vol. 65, No. 12, Sep. 19, 1994, pp. 1507-1509.
J.B. MacChesney et al., “Growth and Electrical Properties of vanadium Dioxide Single Cyrstals Containing Selected Impurity Ions”, J. Phys. Chem. Solids, Pergamon Press 1969, vol. 30, pp. 225-234.
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C.H. Griffiths et al., “Influence of stoichiometry on the metal-semiconductor transition in vanadium dioxide”, J. Appl. Phys., vol. 45, No. 5, May 1974, pp. 2201-2206.

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