Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2007-04-03
2007-04-03
Ngô, Ngân V. (Department: 2818)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S734000
Reexamination Certificate
active
10786440
ABSTRACT:
A method for patterning a magnetic memory cell junction is provided herein, which includes etching exposed portions of a stack of layers to a level spaced above a tunneling barrier layer of the stack of layers. In addition, the method may include implanting dopants into exposed portions of the stack of layers. For example, the method may include oxidizing and/or nitriding the exposed portions of the stack of layers. In some embodiments, the steps of etching and implanting dopants may form an upper portion of the magnetic cell junction. Alternatively, the method may include alternating the steps of etching and implanting dopants throughout the thickness of the exposed portions of the stack of layers. In either case, the stack of layers may include a magnetic layer which includes a material adapted to prevent the introduction of dopants underlying the tunneling barrier layer during the step of implanting.
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International Search Report, application No. PCT/US2004/006149, mailed Sep. 29, 2004.
Chen Eugene Y.
Kula Witold
Ounadjela Kamel
Wolfman Jerome S.
Cypress Semiconductor Corp.
Daffer Kevin L.
Daffer McDaniel LLP
Lettang Mollie E.
Ngo Ngan V.
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