Magnetic memory cell

Details Magnetic memory cell Magnetic memory cell

2003-01-31

2004-06-08

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Passive components in ics

C257S537000, C257S427000

Reexamination Certificate

active

06747335

ABSTRACT:

BACKGROUND OF THE INVENTION
One type of nonvolatile memory device known in the art relies on magnetic memory cells. Referred to as magnetic random access memory (MRAM) devices, these devices include an array of magnetic memory cells. The magnetic memory cells used in an MRAM device may be of several different types. For example, a tunneling magnetic junction (TMJ) memory cell or a giant magnetoresistive (GMR) memory cell.
A typical magnetic memory cell includes a layer of magnetic film in which the orientation of magnetization is alterable and a layer of magnetic film in which the orientation of magnetization is fixed or “pinned” in particular direction. The magnetic film having alterable orientation of magnetization may be referred to as a data storage layer and the magnetic film having an orientation of magnetization which is pinned may be referred to as a reference layer. The data storage layer and the reference layer are separated by a layer of insulating material.
In an MRAM device, conductive traces (commonly referred to as word lines and bit lines, or collectively as write lines) are routed in a matrix across a plurality of memory cells. Word lines extend along rows of the memory cell array, and bit lines extend along columns of the memory cell array. A memory cell is located at each intersection of a word line and a bit line.
Each memory cell stores a bit of information as an orientation of magnetization. Typically, the orientation of magnetization in the data storage layer aligns along an axis of the data storage layer that is commonly referred to as its easy axis. In a “parallel” orientation, the magnetic fields of the data storage layer and the reference layer point in the same direction. In an “anti-parallel” orientation, the magnetic fields of the data storage layer and the reference layer point in opposite directions. External magnetic fields are applied to flip the orientation of magnetization in the data storage layer along its easy axis to either a parallel or anti-parallel orientation with respect to the orientation of magnetization in the reference layer, depending on the desired logic state. The orientation of magnetization of each memory cell will thus assume one of two stable orientations at any given time. These two stable orientations, parallel and anti-parallel, represent logic values of “1” and “0”, respectively.
The orientation of magnetization of a selected memory cell may be changed by supplying currents to the word line and bit line intersecting at the selected memory cell. The currents in the word and bit lines create magnetic fields that, when combined switch the orientation of magnetization of the selected memory cell from parallel to anti-parallel or vice versa. Additionally, the write lines can be used to read the logic values stored in the memory cell.
One problem which exists for MRAM devices using magnetic memory cells like those described above is the occasional presence of a defective memory cell. In particular, the insulating layer of a memory cell may include defects which cause the nominal resistance of the affected memory cell to drop several orders of magnitude lower than the resistance of a properly functioning memory cell. The insulating layer is typically the only non-conductive material in the memory cell stack. Thus, defects such as foreign conductive material particles in the insulating layer, pin holes through the insulating layer, or a too-thin insulating layer resulting from poor material deposition processes during the formation of the memory cell, may result in a memory cell resistance which is unacceptably low.
Because data in a memory cell is written and read by passing electrical currents through the write lines that intersect the memory cell, a memory cell having a nominal resistance which differs substantially from the resistance of a properly functioning memory cell will affect the currents (and thus magnetic fields) intended to write or read data in the memory cell. The low resistance memory cell is effectively rendered unusable. In addition, in the absence of switches or diodes to isolate one memory cell from another, the low resistance memory cell appears essentially as a short-circuit between the word and bit lines which intersect at the defective memory cell. As a result, all other memory cells along the word and bit line of the defective memory cell are also affected and possibly rendered unusable. This can have a significant negative impact on the storage capacity of the memory array.
Currently, in the absence of switches or diodes to isolate one memory cell from another, there is no effective way to repair a defective memory cell exhibiting low nominal resistance, or limit its detrimental effects on other memory cells sharing a common word and/or bit line in the memory array. Although switches or diodes may be added to an MRAM device to isolate one memory cell from another, such a process adds cost and complexity to the device.
SUMMARY OF THE INVENTION
A memory cell which limits or eliminates the detrimental effects of a low nominal resistance memory cell on an array of memory cells in an MRAM device is described herein. One embodiment of a memory cell according to the invention includes a magnetic data storage layer, a magnetic reference layer, and an insulating layer between the data storage layer and the reference layer. A resistive layer having a known electrical resistance is positioned adjacent the insulating layer.


REFERENCES:
patent: 5640343 (1997-06-01), Gallagher et al.
patent: 6400600 (2002-06-01), Nickel et al.
patent: 6456525 (2002-09-01), Perner et al.
patent: 6480411 (2002-11-01), Koganei

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