Active solid-state devices (e.g. – transistors – solid-state diode – Responsive to non-electrical signal – Magnetic field
Reexamination Certificate
2002-05-08
2004-11-02
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Responsive to non-electrical signal
Magnetic field
C257S295000, C257SE27006
Reexamination Certificate
active
06812537
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a magnetic memory device and more particularly to a magnetic memory device which is constructed to store data of multiple bits in a single memory cell.
2. Description of Related Arts
Magnetic Random Access Memory (hereinafter referred to as MRAM) is known as one of the semiconductor memories storing data in a nonvolatile manner. In MRAM, ferromagnetic films are integrated. Magnetization or magnetic vector of the ferromagnetic material is set to correspond to either “1” or “0”, and, in the case of MRAM, digital data is stored in a nonvolatile manner. That is, vectors in magnetic layers represent two states of magnetization within cell.
Technology for storing multivalued information in a single memory cell of magnetic memory is being developed in an attempt to expand memory capacity. Such magnetic memory has been disclosed in Japanese Patent Application Laid-open No. Hei 11-176149 though this publication teaches GMR memory cell which can be set multiple value.
FIG. 16
shows the cross sectional structure of the magnetic memory. The magnetic memory comprises a substrate
101
. Upon substrate
101
, there is formed, in order, a lower electrode
102
, a first magnetic layer
103
, a first non-magnetic spacer layer
104
, a second magnetic layer
105
, a second non-magnetic spacer layer
106
, a third magnetic layer
107
, and an upper electrode
108
. As shown in FIGS.
17
through
19
, magnetization direction of the multiple magnetic layers is controlled individually. The resistance value between the lower electrode
102
and upper electrode
108
varies in accordance with the combination of magnetization directions. That is, the combination has three type, one of which is that all layers
103
,
105
and
107
are magnetized in the same direction (
FIG. 17
, all left direction), another of which is that the magnetized direction of adjacent layers
103
,
105
,
107
is only one different (FIG.
19
:
103
, left magnetized direction,
105
right magnetized direction and
107
right magnetized direction), the other of which is that the magnetized direction of adjacent layers is all different (FIG.
18
). It is thus possible to store three information in a single memory cell. If number of magnetic layers is n (n>=3) in the solo memory cell, the cell can store n value.
SUMMARY OF THE INVENTION
According to the present embodiments, Magnetic memory as claimed in the present invention comprises: first through n-th tunnel insulating layers (n being a natural number of 2 or greater) and first through (n+1)-th magnetic layers, each respectively having first through (n+1)-th magnetization. The i-th tunnel insulating layer (i being an arbitrary integer of 1 or greater but no greater than n) of the first through n-th tunnel insulating layers are provided between the i-th magnetic layer and the (i+1)-th magnetic layer of the first through (n+1)-th magnetic layers Here, the i-th resistance between the i-th magnetic layer and (i+1)-th magnetic layer is R
i
when the i-th magnetization and the (i+1)-th magnetization of the first through (n+1)-th magnetization are in the same direction, and the i-th resistance is R
i
+&Dgr;R
i
when the i-th magnetization and the (i+1)-th magnetization are in opposite directions. This makes it possible to store at least n+1 values or more as data in this magnetic memory.
At this point, it is preferable that each of &Dgr;R
1
, &Dgr;R
2
, . . . , &Dgr;R
n
be different. In this magnetic memory, there can be obtained at least {(n
2
+n+2)/2} resistance values differing with each other between the first magnetic layer and the (n+1)-th magnetic layer depending on the direction of the first through (n+1)-th magnetization. In this magnetic memory, at least {(n
2
+n+2)/2} values or more can be stored as data.
In this magnetic memory, it is preferable that the sum of any progression generated from elements if the group consisting of, &Dgr;R
1
, &Dgr;R
2
, . . . , &Dgr;R
n
be different from each other. This makes it possible in this magnetic memory for the resistance value between the first magnetic layer and the (n+1)-th magnetic layer to beat least 2
n
different values depending on the direction of the first through the (n+1)-th magnetization. In this magnetic memory, at least 2
n
values or more can be stored as data.
Also, it is preferable that each of &Dgr;R
1
, &Dgr;R
2
, . . . , &Dgr;R
n
be substantially equal to any of &Dgr;R, &Dgr;R/2, &Dgr;R/2
2
, . . . , &Dgr;R/2
n−1
given that &Dgr;R is a predetermined resistance. This causes the resistance value between the first magnetic layer and the (n+1)-th magnetic layer to vary linearly depending on the direction of the first through (n+1)-th magnetization in this magnetic memory.
At this point, it is preferable that the magnetic material comprising the first through (n+1)-th magnetic layers be selected so as for each of the above mentioned &Dgr;R
1
, &Dgr;R
2
, . . . , &Dgr;R
n
to be substantially equal to any of &Dgr;R, &Dgr;R/2, &Dgr;R/2
2
, . . . , or &Dgr;R/2
n−1
.
In addition, it is preferable that the film thickness of the first through n-th tunnel insulating layers be set so as for each of these &Dgr;R
1
, &Dgr;R
2
, . . . , &Dgr;R
n
to be substantially equal to any of &Dgr;R, &Dgr;R/2, &Dgr;R/2
2
, . . . , &Dgr;R/2
n−1
.
In addition, it is preferable that the material comprising the first through n-th tunnel insulating layers be set so as for each of the above mentioned &Dgr;R
1
, &Dgr;R
2
, . . . , &Dgr;R
n
is substantially equal to either one of &Dgr;R, &Dgr;R/2, &Dgr;R/2
2
, . . . , &Dgr;R/2
n−1
.
In addition, it is preferable that the area where the i-th tunnel insulating layer comes into contact with the i-th magnetic layer and the area where the i-th tunnel insulating layer comes into contact with the (i+1)-th magnetic layer be set so as for each of these &Dgr;R
1
, &Dgr;R
2
, . . . , &Dgr;R
n
to be substantially equal to any of &Dgr;R, &Dgr;R/2, &Dgr;R/2
2
, . . . , &Dgr;R/2
n−1
.
In addition, it is preferable that the film quality of the first through n-th tunnel insulating layers be set so as for each of the these &Dgr;R
1
, &Dgr;R
2
, . . . , &Dgr;R
n
to be substantially equal to any of &Dgr;R, &Dgr;R/2, &Dgr;R/2
2
, . . . , &Dgr;R/2
n−1
.
In addition, it is preferable that each of these &Dgr;R
1
, &Dgr;R
2
, . . . , &Dgr;R
n
be substantially equal to any of &Dgr;R
, 2&Dgr;R
, 3&Dgr;R
, . . . , (n−1) &Dgr;R
, &Dgr;R given that &Dgr;R is a predetermined resistance. This makes it possible for {(n
2
+n+2)/2} values to be stored as data in this magnetic memory depending on the direction of first through (n+1)-th magnetization. Moreover, in this magnetic memory, the resistance value between the first magnetic layer and the (n+1)-th magnetic layer varies linearly.
In addition, it is preferable that the direction of the first magnetization be fixed.
At this point, it is preferable that the magnetic memory further comprise an antiferromagnetic layer connected to the first magnetic layer and that the direction of the first magnetization be fixed due to the interaction with the antiferromagnetic layer.
As to aspect of the embodiments of the present invention, a magnetic memory as claimed in the present invention comprises:
(a) a step of directing in a first direction the j-th though the (n+1)-th magnetization (j being an integer of 1 or greater but no greater than n) of the first through (n+1)-th magnetization; and
(b) a step of directing a (j+1)-th through (n+1)-th magnetization of the first through (n+1)-th magnetization, after the (a) step, either in the first direction or a second direction, which is substantially opposite the first direction.
As to another aspect of the embodiments of the present invention, a magnetic memory comprises a memory cell having at least a first ma
Okazawa Takeshi
Suemitsu Katsumi
Ho Tu-Tu
NEC Electronics Corporation
Nelms David
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