Static information storage and retrieval – Addressing – Using selective matrix
Reexamination Certificate
1999-11-19
2002-03-19
Elms, Richard (Department: 2824)
Static information storage and retrieval
Addressing
Using selective matrix
C365S173000, C365S210130, C365S213000, C365S189070
Reexamination Certificate
active
06359829
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a magnetic memory of the random access type (MRAM) containing a memory cell array consisting of a multiplicity of memory cells which are disposed in the form of a matrix at the points of intersection of word lines and sense lines and the logical data contents of which are defined by a magnetic state. The magnetic memory further contains an addressing circuit allocated to the word lines, by which a voltage is applied to the word line of one or more selected memory cells, the data contents of which are to be read out. The magnetic memory also has an evaluation circuit allocated to the sense lines, by which a signal corresponding to the data contents of the selected memory cell or memory cells is acquired and evaluated, respectively.
In such magnetic memories organized as a matrix, the data information is contained in an information carrier layer of the magnetic memory cells disposed at the points of intersection of the word lines and the sense lines in the form of a direction of magnetization. To read out a memory cell, a read voltage is applied either to the sense line or to the word line (always the word line in the text which follows) and via the word line or sense line the signal determined by the impedance of the memory cell which reflects the memory state is evaluated by an associated word line or sense line amplifier circuit.
In this configuration, the relative difference in the impedance of the memory cell depending on the information content (“one” or “zero”) is typically approximately 20% which represents a comparatively low value. To make matters worse for determining the difference in impedance all other memory cells form parallel paths to the memory cell to be read out, thus forming a large parasitic impedance, which weakens the effect of the difference in impedance of the memory cell to be read out by orders of magnitude even with only 100 elements per word line, which has a disadvantageous effect on the signal picked up via the sense lines (sense signal) which is analyzed by a subsequent evaluation circuit.
The manufacture of magnetic memories is affected by fluctuations in the absolute impedances of the memory cells within a batch, a wafer and also within the memory cell array of an individual magnetic memory. The consequence of this is that absolute impedance measurements do not represent a useful starting point for determining the memory state of the memory cell to be read out.
One procedure for determining the memory content of a memory cell that has been known hitherto is now described. The memory cell is read out by activating the associated word lines and sense lines and applying a read voltage to the memory cell and evaluating the signal of the memory cell. The measurement signal thus obtained is temporarily stored, for example capacitively. Following this, a known value (“Tone” or “zero”) is newly written into the memory cell, read out again and the new measurement signal is compared with the measurement signal temporarily stored in order to be able to determine by this the actual memory state. The disadvantageous factor is here obviously that the procedure involves a number of steps.
In a further previously known approach, magnetic reference layers located within the memory cell are used. In this case, a distinction can again be made between permanent and variable magnetic reference layers. Since in the case of permanent magnetic reference layers the same problems with the fluctuations of the absolute impedances as already described above occur they will not be considered in greater detail here. In order to read out a memory cell, magnetic reference layers with a variable magnetic orientation can be magnetically orientated in a defined direction (reference direction) by a current through the word line or sense line. In this case, the change in direction of the orientation, and thus of the absolute impedance, is evaluated instead of the absolute impedance value. The direction of magnetization of the information carrier layer, which can be equated with the data contents, is retained in this case and the reference layer that is magnetized relatively softly is remagnetized. It is also possible to use a memory in which the reference layer is the magnetically harder layer and the information carrier layer is switched over.
All previously known methods and memories have the disadvantage that the information of the memory cell is read out by successively occurring processes resulting in a relatively great time expenditure.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a magnetic memory which overcome the above-mentioned disadvantages of the prior art devices and methods of this general type, in which there is no loss of time due to successively occurring processes or method-associated rewriting of the information and which provides for data processing which is independent of fluctuations in the absolute impedances of the memory cells due to manufacture.
With the foregoing and other objects in view there is provided, in accordance with the invention, a random access type magnetic memory (MRAM), including:
word lines;
sense lines;
a memory cell array containing a multiplicity of memory cells disposed in a matrix at points of intersection of the word lines and the sense lines and having logical data contents being defined by a magnetic state;
an addressing circuit connected to the word lines for applying a read voltage to a word line of a selected memory cell in which the logical data contents are to be read out as a sense signal on one of the sense lines;
a reference element outputting a reference signal; and
an evaluation circuit connected to the sense lines and having a comparator circuit receiving the sense signal and the reference signal supplied by the reference element and compares the reference signal with the sense signal generated from the selected memory cell being read out.
According to the invention, it is provided that the evaluation circuit has a comparator circuit by which a reference signal supplied by a reference element is compared with the sense signal of the selected memory cell or memory cells. The invention proposes to render the read-out process independent of the influences of the fluctuation of the absolute impedances of the wafer or of the batch by providing a reference element formed on the memory chip. This makes it possible to read out the information of the memory cell without the great fluctuations of the absolute impedances having an effect. This is achieved by forming a difference signal in the comparator circuit with the sense signal of the memory cell and the reference signal of the reference cell.
In this configuration, the comparator circuit is suitably formed by a differential amplifier which is associated with a resistor, one end of which is connected to one input and the other end of which is connected to the output of the differential amplifier and resistors are connected in series with the inputs of the differential amplifier.
In an advantageous development of the invention, the word lines and sense lines can be individually connected to ground by grounding switches. The advantage resulting from this is that the multiplicity of parasitic elements formed by the totality of the memory cells is distinctly reduced if the word lines and sense lines not needed for acquiring the signal are grounded.
The reference element can be advantageously constructed in such a manner that the electrical and magnetic characteristics, respectively, are matched to the characteristics of the memory cell(s) and, if necessary, is adjusted to those of the memory cells by varying the same characteristics and, in addition, is disposed outside the memory cell array. The reference element is advantageously connected directly to the reference amplifier circuit which processes the signal of the reference cell to become the reference signal.
If the magnetic and electrical characteristics, respectively, of the memory cells within a memory cell arr
Elms Richard
Greenberg Laurence A.
Infineon - Technologies AG
Lerner Herbert L.
Nguyen Tuan T.
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