Dynamic magnetic information storage or retrieval – General processing of a digital signal – Pulse crowding correction
Reexamination Certificate
2002-02-12
2004-07-06
Faber, Alan T. (Department: 2651)
Dynamic magnetic information storage or retrieval
General processing of a digital signal
Pulse crowding correction
C360S053000, C360S065000
Reexamination Certificate
active
06760171
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to a method and apparatus for delaying an electronic signal transition, and, more particularly, to delaying signal transitions written to a magnetic storage medium in a way that reduces or eliminates non-linear bit shifts during a subsequent read operation.
BACKGROUND OF THE INVENTION
Conventional magnetic storage devices typically read and write data onto one or more data tracks in a magnetic storage medium. In a conventional hard disk drive, for example, the data tracks are concentric rings on one or both surfaces of a disk or plurality of disks. To write data to a track, the disk is rotated at a predetermined rate and a magnetic write head floating over the track transforms electrical signals representative of the data to be written to magnetic field transitions on the track which similarly represent the data. A small magnetic domain on the track represents each bit. Shifting the orientation of magnetization from one domain to another creates “transitions.” When a floating magnetic read head passes over transition, the read head produces an electrical pulse.
Digital data is thus stored on conventional magnetic storage devices as the presence or absence of magnetic transitions. When read, the transitions generate a magnetic pulse at a bit time may represent a bit value of one and the absence of a pulse may represent a bit value of zero, for example. A bit clock, which determines the bit time, may be embedded in the data and recovered upon reading data from the disk, for example. Various encoding schemes may be employed in the storage of such data. Non-return to zero inverted (NRZI) encoding, for example, employs a pulse to represent a one and the absence of a pulse to represent a zero. A string of three ones would therefore be represented as three consecutive shifts in the orientation of magnetization in the magnetic medium.
A variety of imperfections, such as inter-symbol interference, pulse compression, pulse-edge displacement or non-linear transition shifts due to non-linearities in the recording medium, may shift transitions, or pulses, from their nominal “bit-time” locations. Various methods have been employed to precompensate for these imperfections. Precompensation schemes are discussed, for example, in U.S. Pat. No. 6,133,861 issued to Jusuf et. al., and U.S. Pat. No. 6,157,506 issued to Ueno, both of which are hereby incorporated by reference in their entirety. Precompensation approaches typically delay a write signal in order to shift the location of the data domain written by the write head, thereby positioning the domain closer to a compensated position, that is, a position which results in a read bit being coincident with a bit time.
However, conventional precompensation schemes provide only limited flexibility in the selection of delays, thereby limiting the amount by which a written magnetic domain may be shifted and, therefore, limiting the amount of precompensation available. A flexible system and method for precompensating disk write signals would therefore be highly desirable.
SUMMARY
In a system and method in accordance with the principles of the present invention, a magnetic medium write precompensation circuit produces a precisely controlled delay for magnetic medium write precompensation by digital-to-analog converting a data value (which may be encoded), low-pass filtering the digital-to-analog converted signal, and limiting the filtered signal to produce a desired time delay corresponding to a desired positional shift of the signal transition as written to the magnetic medium. For a given limiting level, the degree to which the amplitude of the signal transition is adjusted determines the amount of the delay. That is, a “partial amplitude” signal is added to a signal, then filtered. The filtered resultant signal is limited at a level that provides a desired time-compensation for an output write signal.
In an illustrative embodiment, converting a single-bit data value to a multi-bit value, then converting the multi-bit value to a multi-level output signal via a digital-to-analog converter (DAC) produces the “partial amplitude” signal. The single-bit value may be referred to as a one or a zero may be represented by high or low voltage values, positive or negative current, and may employ positive or negative logic. Depending upon circuit timing, the multi-level output signal may take the form of a single output at one of several possible levels or it may be a series of signals at a variety of the possible output levels, with the filtered signal limited at a level that provides a desired write delay.
REFERENCES:
patent: 4725901 (1988-02-01), Eiberger
patent: 6091558 (2000-07-01), Voorman
patent: 6133861 (2000-10-01), Jusuf et al.
patent: 6157506 (2000-12-01), Ueno
patent: 6212024 (2001-04-01), Igarashi
Faber Alan T.
Guzik Technical Enterprises
McDermott & Will & Emery
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