Communications: electrical – Digital comparator systems
Patent
1974-07-12
1976-03-16
Urynowicz, Jr., Stanley M.
Communications: electrical
Digital comparator systems
340174SR, 340174M, G11C 1114, G11C 1908
Patent
active
039449912
ABSTRACT:
The insertion of new data into a major-minor loop memory is effected by selectively controlling the passage of bubbles through at least two gates provided between a bubble generator and the major loop. In a two-dimensional array of such memories, the write process is initiated by first applying a transfer signal to a selected row of the memories to transfer the data in the row into their respective major loops for subsequent erasure. Then, a gate signal is applied to a first gate of each memory in the selected row to condition it for write. Another gate signal is applied to a second gate of each memory in a selected column in accordance with the data to be inserted. This arrangement permits new data to be inserted into only the memory of the array that is located at the intersection of the selected row and column.
REFERENCES:
patent: 3701132 (1972-10-01), Bonyhard et al.
patent: 3792450 (1974-02-01), Bogar et al.
Nippon Electric Company Ltd.
Urynowicz, Jr. Stanley M.
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