Magnetic bubble memory circuit with input swap and output replic

Static information storage and retrieval – Magnetic bubbles – Generators

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365 7, 365 11, 365 15, 365 33, G11C 1908

Patent

active

041527763

ABSTRACT:
Magnetic bubble domain memory circuit in which magnetizable overlay patterns of magnetically soft material, e.g. permalloy, are provided as bubble propagation elements on a bubble-supporting magnetic layer to define major and minor bubble propagation paths. The bubble propagation elements are arranged to form major propagation paths defining a bubble input section and a bubble output section respectively. A plurality of minor propagation paths in the form of closed storage loops defining a bubble storage section are disposed between the input and output bubble sections, being arranged in even and odd blocks of minor propagation paths. Input swap transfer gates and output replicate gates are provided between the bubble storage loops and the input and output sections respectively. The input swap transfer gates and the output replicate gates are of double level construction, each type of gate including a hairpin element at the first level and a 90.degree. hook-like element at the second level which is correlated into bubble propagation elements included in a minor storage loop. The 90.degree. hook-like elements of corresponding swap transfer and replicate gates are respectively situated at the input and output ends of the minor storage loops, forming the opposite bights of the loop. Bubble generators and detectors are associated with the input and output bubble sections respectively at the opposite ends of the minor storage loops to provide a magnetic bubble domain memory chip for data processing purposes. Data as represented by the presence or absence of a magnetic bubble is transferred into the minor storage loops and replicated outwardly therefrom into the bubble output section for detection in a manner enabling such data to be received by the bubble detector for readout at the field rate.

REFERENCES:
patent: 4007453 (1977-02-01), Bonyhard et al.
patent: 4020476 (1977-04-01), Bonyhard et al.
AIP Conference Proceedings, "64 Fast Access Chip Design", No. 29, pp. 51-53, Dec. 9-12, 1975.

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