Macroscalar processor architecture

Details Macroscalar processor architecture Macroscalar processor architecture

2005-09-01

2009-11-10

Coleman, Eric (Department: 2183)

Data processing: software development, installation, and managem

Software program development tool

Translation of code

C712S241000

Reexamination Certificate

active

07617496

ABSTRACT:
A macroscalar processor architecture is described herein. In one embodiment, a processor receives instructions of a program loop having a vector block and a sequence block intended to be executed after the vector block, where the processor includes multiple slices and each of the slices is capable of executing an instruction of an iteration of the program loop substantially in parallel. For each iteration of the program loop, the processor executes an instruction of the sequence block using one of the slices while executing instructions of the vector block using a remainder of the slices substantially in parallel. Other methods and apparatuses are also described.

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