Macrocell with product-term cascade and improved flip flop utili

Details Macrocell with product-term cascade and improved flip flop utili Macrocell with product-term cascade and improved flip flop utili

1993-01-28

1994-10-18

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307243, H03K 19177

Patent

active

053571533

ABSTRACT:
A programmable logic device having macrocells enables gate cascades between macrocells to occur with a faster signal transit time, while preserving the flip flop function of the cascaded macrocells by reallocating a redirectable flip flop reset product term to the flip flop input. All gate product terms are retained during cascading. The macrocell logic is optimized for fast signal transit with selectable flip flop clocking. Multiplex clocking and programming are done with fewer transistors in the signal path, further reducing signal transit time.

REFERENCES:
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patent: 4912345 (1990-03-01), Steele et al.
patent: 4933577 (1990-06-01), Wong et al.
patent: 5027011 (1991-06-01), Steele
patent: 5027315 (1991-06-01), Agrawal et al.
patent: 5121006 (1992-09-01), Pederson
patent: 5136188 (1992-08-01), Ha et al.
patent: 5260611 (1993-11-01), Cliff et al.
patent: 5309046 (1994-05-01), Steele
Mach Family Data Book, "Mach 1 and Mach 2 Families", Q2 1991 Data Book, available from Advanced Micro Devices, Inc.

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