Macrocell array having an on-chip clock generator

Details Macrocell array having an on-chip clock generator Macrocell array having an on-chip clock generator

1983-07-01

1986-06-03

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307467, 307601, 307602, 307608, 307303, 307455, 357 45, 357 68, H03K 5135, H03K 514, H03K 19086, H01L 2710

Patent

active

045932050

ABSTRACT:
A macrocell array is provided wherein a plurality of cells, each having a plurality of semiconductor devices interconnected for providing logic functions, are selectively interconnected to one another and to input/output pads by a plurality of horizontal and vertical routing channels in one or more metallization layers. An on-chip clock generator is provided within one of the cells and comprises a gate means responsive to an input signal and providing a delayed signal. An output means is coupled to the gate means and is responsive to the input signal and the delayed signal for generating a clock pulse. The gate means includes two or more serially connected sets of differentially connected transistors wherein the time between the input signal and the delayed signal is the summation of the propagation delays of the two or more serially connected sets of differentially connected transistors. External override signals allow for control of the clock pulse regardless of the state of the input signal.

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Mukai et al., "Master Slice ECL LSI"; Review of the Electrical Communication Laboratories; vol. 26, Nos. 9-10/Sep.-Oct. 1978; pp. 1325-1338.
Lee et al., "A 2500-Gate Bipolar Macro Cell Array With 250 ps Gate Delay"; IEEE-ISSCC 82; 2/11/1982; Digest of Technical Papers, pp. 178-179.

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