Macro structural arrangement and method for generating macros fo

Details Macro structural arrangement and method for generating macros fo Macro structural arrangement and method for generating macros fo

1987-06-19

1989-07-18

Arnold, Bruce Y.

Boots, shoes, and leggings

364488, G06F 1560

Patent

active

048499048

ABSTRACT:
A macro generation method and a macro structural arrangement are provided for a VLSI semiconductor circuit device. A circuit macro is defined by a plurality of circuit blocks including at least one control block and an identified number of storage blocks. The control block includes a control section, a bit decoder section, a word decoder section and a work selector section. Each of the storage blocks includes a memory section, a bit selector section and a sense latch driver section. One of a plurality of stored predetermined bit decoders is selectively provided for the bit decoder section. A required number of storage blocks is identified responsive to the selected bit decoder for the selected number of bits per word. A required number of word selectors and memory array subsections is identified responsive to the selected bit decoder for the selected number of words.

REFERENCES:
patent: 4596003 (1986-06-01), Shimizu
patent: 4598386 (1986-07-01), Roesner et al.
patent: 4602339 (1986-07-01), Aihara etr al.
patent: 4694433 (1987-09-01), Wiedmann
patent: 4724531 (1988-02-01), Angleton et al.

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