Macro cell

Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays

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Details

257208, 257773, H01L 2710

Patent

active

060910887

ABSTRACT:
A macro cell of field effect transistors includes source-drain areas respectively divided into a contact area and a non-contact area. One source-drain area of two of the source-drain areas located on opposite sides of the effective width portion of a gate electrode has a contact area at an upper portion and a non-contact area at a lower portion while the other source-drain area has the non-contact area at its upper portion and the contact area at its lower portion. The distance between effective width portions of gate electrodes where the non-contact area is located is smaller than the distance between effective width portions of gate electrodes where the contact area is located.

REFERENCES:
patent: 4905073 (1990-02-01), Chen et al.
Itoh et al., "Session XIV: Array And Gb Logic", IEEE International Solid-State Circuits Conference, Feb. 1982, pp. 176-177.

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