Macro block address processor for digital compressed video signa

Details Macro block address processor for digital compressed video signa Macro block address processor for digital compressed video signa

1993-05-14

1994-10-25

Chin, Tommy P.

Television

Bandwidth reduction system

H04N 7130

Patent

active

053594207

ABSTRACT:
A macro block address processor for a digital compressed video signal decoder, comprising input run/level memories for storing a zero run value and a level value for each macro block coefficient data from a decoding section, respectively, an absolute macro block address generator for converting relative macro block addresses inputted therein into absolute macro block addresses using a slice start code, an absolute macro block address memory for storing an output signal from the absolute macro block address generator, a macro block address counter for sequentially counting macro black addresses by one slice in response to a macro black clock, a comparator for comparing an output signal from the absolute macro block address memory with an output signal from the macro block address counter, a read control let for controlling a read operation of the absolute macro block address memory in response to an output signal from the comparator, and a multiplexer for selecting one of the zero run value from the run memory and a zero run value from one of the level value from said level memory means, or for selecting a zero run value from zero setting means and a level value from said zero setting means in response to the output signal from the comparator and outputting the selected values to a coefficient generator.

REFERENCES:
patent: 5121205 (1992-06-01), Ng et al.
patent: 5146325 (1992-09-01), Ng
patent: 5212549 (1993-05-01), Ng et al.
patent: 5241382 (1993-08-01), Paik et al.

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