Macro assembler process for automated circuit design

Details Macro assembler process for automated circuit design Macro assembler process for automated circuit design

1980-12-29

1983-03-22

Wise, Edward J.

Boots, shoes, and leggings

364300, 307303, G06F 1546

Patent

active

043778496

ABSTRACT:
A process automatically generating topology data for fabricating large scale integrated circuits. Technology data, a logic function description and logic circuit components are generated and input to a data processing system together with geometric dimension data descriptive of the basic elements of the logic circuit components. The geometric dimension data is assembled into a plurality of intermediate level geometric topology patterns under control of the logic function description and the intermediate level geometric topology patterns are assembled into a prime level geometric topology representative of the logic function description. The logic circuit components are merged with the prime level geometric topology to produce a grid array to be fabricated into a large scale integrated circuit.

REFERENCES:
patent: T938005 (1975-09-01), Colton et al.
patent: T940020 (1975-11-01), Brechling et al.
patent: 3475621 (1969-10-01), Weinberger
patent: 3567914 (1971-03-01), Neese et al.
patent: 3653071 (1972-03-01), Hill et al.
patent: 3653071 (1972-03-01), Hill et al.
patent: 3968478 (1976-07-01), Mensch, Jr.
The Automatic Design of Interconnection Patterns for Large Scale Integration; P. E. Radley; International Conference on Computer Aided Design, Apr. 15-18, 1969.
Producing Integrated Circuits from a Circuit Logic Input; O. Bilous, et al, IBM Technical Disclosure Bulletin, vol. 13, No. 5, Oct. 1970, pp. 1084-1089.
Relating Logic Design to Physical Geometry in LSI Chip; K. W. Lallier & A. D. Savkar, IBM Technical Disclosure Bulletin, vol. 19, No. 6, Nov. 1976, pp. 2140-2143.
Incremental Masterslice Part Number Design; B. C. Fox & W. R. Kraft; IBM Technical Disclosure Bulletin, vol. 20, No. 3, Aug. 1977, pp. 1116-1119.

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