Mac processor with efficient Viterbi ACS operation and automatic

Details Mac processor with efficient Viterbi ACS operation and automatic Mac processor with efficient Viterbi ACS operation and automatic

1997-11-14

1999-11-16

Malzahn, David H.

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

371 437, G06F 738

Patent

active

059874902

ABSTRACT:
A dual-MAC processor optimized so that two Viterbi ACS operations, including traceback bit storage, can be executed in two machine cycles is disclosed. The processor comprises a pair of adder arithmetic logic units connected to a common accumulator register bank and supporting full and split-mode add, subtract, and compare operations. Viterbi compare operations are executed using the subtract function and the sign bit is combined with a compare mode bit to generate a traceback output which indicates the proper traceback bit to store. When a compare operation is performed and a Viterbi mode bit is active, each generated traceback output is shifted into a traceback register for later use in a Viterbi traceback routine.

REFERENCES:
patent: 5377133 (1994-12-01), Riggle et al.
patent: 5450338 (1995-09-01), Oota et al.
patent: 5502736 (1996-03-01), Todoroki
patent: 5633897 (1997-05-01), Fettweis et al.
patent: 5751734 (1998-05-01), Choi et al.
patent: 5781569 (1998-07-01), Fossorier et al.
Users guide, Texas Instruments TMS320C54X "1995 Preliminary Digital Signal Processing Products", Nov. 6, 1997, pp. 2.2, 3.15-3.17, 8.64, and 12.47-12.50.
Henry Hendrix, "Viterbi Decording Techniques in the TMS320C54X", pp. 1-19, Jun. 1996.

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